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參數(shù)資料
| 型號(hào)： | AD5439 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行DAC |
| 英文描述： | Dual 10-Bit High Bandwidth Multiplying DACs with Serial Interface |
| 中文描述： | 雙通道、10位、高帶寬、串行接口乘法DAC |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 860K |
| 代理商： | AD5439 |
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AD5429/AD5439/AD5449
SERIAL INTERFACE
The AD5429/AD5439/AD5449 have an easy to use, 3-wire
interface that is compatible with SPI, QSPI, MICROWIRE, and
DSP interface standards. Data is written to the device in 16-bit
words. This 16-bit word consists of 4 control bits and either
8, 10, or 12 data bits, as shown in Figure 43, Figure 44, and
Figure 45.
Low Power Serial Interface
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC. The SCLK and DIN input buffers
are powered down on the rising edge of SYNC.
DAC Control Bits C3–C0
Control bits C3 to C0 allow control of various functions of
the DAC, as shown in Table 11. Default setting of the DAC at
power-on are as follows.
Rev. 0 | Page 20 of 32
Data is clocked into the shift register on falling clock edges;
daisy-chain mode is enabled. The device powers on with zero-
scale load to the DAC register and I
OUT
lines. The DAC control
bits allow the user to adjust certain features at power-on; for
example, daisy-chaining can be disabled if not in use, active
clock edge can be changed to rising edge, and DAC output can
be cleared to either zero scale or midscale. The user can also
initiate a readback of the DAC register contents for verification.
Control Register (Control Bits = 1101)
While maintaining software compatibility with the single-
channel current output DACs (AD5426/AD5432/AD5443),
these DACs also feature some additional interface functionality.
Set the control bits to 1101 to enter control register mode.
Figure 46 shows the contents of the control register. The
following sections describe the functions of the control register.
SDO Control (SDO1 and SDO2)
The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an open-
drain driver. The strength of the SDO driver affects the timing
of t
12
, and, when stronger, allows a faster clock cycle.
Table 10. SDO Control Bits
SDO2
0
0
1
1
SDO1
0
1
0
1
Function Implemented
Full SDO driver
SDO configured as open-drain
Weak SDO driver
Disable SDO output
Daisy-Chain Control (DSY)
DSY allows the enabling or disabling of daisy-chain mode.
A 1 enables daisy-chain mode, and 0 disables daisy-chain mode.
When disabled, a readback request is accepted, SDO is auto-
matically enabled, the DAC register contents of the relevant
DAC are clocked out on SDO, and, when complete, SDO is
disabled again.
Hardware CLR Bit (HCLR)
The default setting for the hardware CLR bit is to clear the
registers and DAC output to zero code. A 1 in the HCLR bit
allows the CLR pin to clear the DAC outputs to midscale and
a 0 clears to zero scale.
Active Clock Edge (SCLK)
The default active clock edge is falling edge. Write a 1 to this bit
to clock data in on the rising edge, or a 0 for falling edge.
DATA BITS
CONTROL BITS
C3
C2
C1
C0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
DB0 (LSB)
DB15 (MSB)
0
Figure 43. AD5429 8-Bit Input Shift Register Contents
DATA BITS
CONTROL BITS
C3
C2
C1
C0
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
DB0 (LSB)
DB15 (MSB)
0
Figure 44. AD5439 10-Bit Input Shift Register Contents
DATA BITS
CONTROL BITS
C3
C2
C1
C0
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB0 (LSB)
DB15 (MSB)
0
Figure 45. AD5449 12-Bit Input Shift Register Contents
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