參數(shù)資料
型號(hào)： AD5429YRU-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/29頁(yè)
文件大?。?/td> 0K
描述： IC DAC DUAL 8BIT MULT 16-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時(shí)間： 30ns
位數(shù)： 8
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 3.5µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 2.47M
Data Sheet
AD5429/AD5439/AD5449
Rev. E | Page 17 of 28
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 40 shows the DACs operating in voltage-switching mode.
The reference voltage, VIN, is applied to the IOUT1A pin; IOUT2A
is connected to AGND; and the output voltage is available at the
VREFA terminal. In this configuration, a positive reference voltage
results in a positive output voltage, making single-supply operation
possible. The output from the DAC is voltage at a constant
impedance (the DAC ladder resistance). Therefore, an op amp
is necessary to buffer the output voltage. The reference input
no longer sees a constant input impedance; instead, it sees one
that varies with code. Therefore, the voltage input should be
driven from a low impedance source.
Note that VIN is limited to low voltages because the switches
in the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and degrades the
integral linearity of the DAC. Also, VIN must not go negative by
more than 0.3 V, or an internal diode turns on, causing the device
to exceed the maximum ratings. In this type of application, the
full range of multiplying capability of the DAC is lost.
Positive Output Voltage
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier because
of the resistor tolerance errors. To generate a negative reference,
the reference can be level-shifted by an op amp such that the VOUT
and GND pins of the reference become the virtual ground and
2.5 V, respectively, as shown in Figure 41.
VOUT
VDD
GND
VIN
IOUT2A
IOUT1A
RFBA VDD
VREFA
R2
R1
04464-
009
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
8-/10-/12-BIT
DAC
Figure 40. Single-Supply Voltage-Switching Mode
VOUT = 0V TO +2.5V
VDD = +5V
GND
IOUT2A
IOUT1A
RFBA
VDD
VREFA
C1
GND
VIN
VOUT
ADR03
+5V
–5V
8-/10-/12-BIT
DAC
–2.5V
04464-010
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 41. Positive Voltage Output with Minimum Components
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