參數(shù)資料
型號： AD5426YRM-REEL7
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
中文描述： SERIAL INPUT LOADING, 0.09 us SETTLING TIME, 8-BIT DAC, PDSO10
封裝： 3 X 5 MM, MSOP-10
文件頁數(shù)： 5/32頁
文件大?。?/td> 860K
代理商： AD5426YRM-REEL7
AD5429/AD5439/AD5449
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V, V
REF
= 5 V, I
OUT
2 = 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Rev. 0 | Page 5 of 32
See Figure 2 and Figure 3. Temperature range for Y version is 40°C to +125°C. Guaranteed by design and characterization, not subject to
production test. All input signals are specified with tr = tf = ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Table 2.
Parameter
f
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
122
1
Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
2
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 4.
Limit at T
MIN
, T
MAX
50
20
8
8
13
5
4
5
30
0
12
10
25
60
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
1
Max clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
相關PDF資料
PDF描述
AD5432BRM 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5432YRM 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5432YRM-REEL 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5432YRM-REEL7 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5440 Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
相關代理商/技術參數(shù)
參數(shù)描述
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AD5428 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
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