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參數(shù)資料
| 型號： | AD5425YRMZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT MULTIPLYING 10MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 設(shè)置時間： | 15ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 25µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 9.5M |
| 配用： | EVAL-AD5425EBZ-ND - BOARD EVALUATION FOR AD5425 |
Data Sheet
AD5425
Rev. C | Page 15 of 24
Figure 31. Bipolar Operation (4-Quadrant Multiplication)
Bipolar Operation
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors, as shown in Figure 31.
In this circuit, the second amplifier, A2, provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage, results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data, D, is
incremented from code zero (VOUT = VREF) to midscale
(VOUT = 0 V ) to full scale (VOUT = +VREF).
(
)
REF
n
REF
OUT
V
D
V
×
=
1
2
/
Where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation.
Table 6. Bipolar Code Table
Digital Input
Analog Output (V)
1111 1111
+V
REF (127/128)
1000 0000
0
0000 0001
V
REF (127/128)
0000 0000
V
REF (128/128)
Stability
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as closely as
possible and proper PCB layout techniques must be employed.
Since every code change corresponds to a step function, gain
peaking can occur if the op amp has limited GBP and there
is excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in closed-loop
applications.
An optional compensation capacitor, C1, can be added in
Figure 31. Too small a value of C1 can produce ringing at the
output, while too large a value can adversely affect the settling
time. C1 should be found empirically, but 1 pF to 2 pF is
generally adequate for compensation.
VOUT = –VREF
TO +VREF
SCLK SDIN GND
VREF
±10V
SYNC
IOUT2
IOUT1
RFB
AGND
AD5425
R1
R2
A1
VREF
VDD
C1
NOTES:
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR
VOUT = 0 V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH
SPEED AMPLIFIER.
MICROCONTROLLER
R4
10k
R5
20k
R3
20k
A2
A1
03161-031
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