參數(shù)資料
型號: AD5425YRM-REEL
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 8-Bit, High Bandwidth Multiplying DAC with Serial Interface
中文描述: SERIAL INPUT LOADING, 0.09 us SETTLING TIME, 8-BIT DAC, PDSO10
封裝: MO-187BA, MSOP-10
文件頁數(shù): 16/20頁
文件大?。?/td> 417K
代理商: AD5425YRM-REEL
REV. 0
–16–
AD5425
SCLK
SK
MICROWIRE
*
SYNC
CS
SDIN
SO
AD5425
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. MICROWIRE to AD5425 Interface
PIC16C6x/7x to AD5425
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual
.
In this example, I/O port RA1 is being used to provide a
SYNC
signal and enable the serial port of the DAC. This
microcontroller transfers eight bits of data during each serial
transfer operation. Figure 16 shows the connection diagram.
SCLK
SCK/RC3
PIC16C6x/7x
*
SYNC
RA1
SDIN
SDI/RC4
AD5425
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. PIC16C6x/7x to AD5425 Interface
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5425 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of the
board. If the DAC is in a system where multiple devices require
an AGND-to-DGND connection, the connection should be
made at one point only. The star ground point should be estab-
lished as close as possible to the device.
These DACs should have ample supply bypassing of 10
μ
F in
parallel with 0.1
μ
F on the supply located as close to the pack-
age as possible, ideally right up against the device. The 0.1
μ
F
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1
μ
F to 10
μ
F tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and to filter out low frequency ripple.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board, and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane while signal traces are
placed on the solder side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between V
REF
and R
FB
should also be
matched to minimize gain error. To maximize on high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
EVALUATION BOARD FOR THE AD5425 DAC
The board consists of an 8-bit AD5425 and a current to voltage
amplifier AD8065. Included on the evaluation board is a 10 V
reference ADR01. An external reference may also be applied via
an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows the
user to write a code to the device.
OPERATING THE EVALUATION BOARD
Power Supplies
The board requires 12 V, and +5 V supplies. The +12 V V
DD
and V
SS
are used to power the output amplifier, while the +5 V
is used to power the DAC (V
DD1
) and transceivers (V
CC
).
Both supplies are decoupled to their respective ground plane
with 10
μ
F tantalum and 0.1
μ
F ceramic capacitors.
Link1 (LK1) is provided to allow selection between the on-board
reference (ADR01) or an external reference applied through J2.
Link2 should be connected to
LDAC
position.
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