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| 型號(hào)： | AD5425YRM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 8-Bit, High Bandwidth Multiplying DAC with Serial Interface |
| 中文描述： | SERIAL INPUT LOADING, 0.09 us SETTLING TIME, 8-BIT DAC, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 417K |
| 代理商： | AD5425YRM-REEL7 |
REV. 0
–12–
AD5425
Bipolar Operation
In some applications, it may be necessary to generate full 4-quadrant
multiplying operation or a bipolar output swing. This can be
easily accomplished by using another external amplifier and some
external resistors as shown in Figure 5. In this circuit, the second
amplifier A2 provides a gain of 2. Biasing the external amplifier
with an offset from the reference voltage results in full 4-quadrant
multiplying operation. The transfer function of this circuit shows
that both negative and positive output voltages are created as the
input data (D) is incremented from code zero (V
OUT
= –V
REF
)
to midscale (V
OUT
= 0 V ) to full scale (V
OUT
= + V
REF
).
(
V
V
V
OUT
REF
REF
=
×
)
D
n
/
–
2
1
Where
D
is the fractional representation of the digital word loaded
to the DAC and
n
is the resolution of the DAC.
When V
IN
is an ac signal, the circuit performs 4-quadrant
multiplication.
Table II shows the relationship between digital code and the
expected output voltage for bipolar operation.
Table II. Bipolar Code Table
Digital Input
Analog Output (V)
1111 1111
1000 0000
0000 0001
0000 0000
+V
REF
(127/128)
0
–V
REF
(127/128)
–V
REF
(128/128)
Stability
In the I-to-V configuration, the I
OUT
of the DAC and the inverting
node of the op amp must be connected as close as possible, and
proper PCB layout techniques must be employed. Since every
code change corresponds to a step function, gain peaking may
occur if the op amp has limited GBP and there is excessive para-
sitic capacitance at the inverting node. This parasitic capacitance
introduces a pole into the open-loop response, which can cause
ringing or instability in closed-loop applications.
An optional compensation capacitor, C1 can be added in parallel
with R
FB
for stability as shown in Figures 6 and 7. Too small a
value of C1 can produce ringing at the output, while too large a
value can adversely affect the settling time. C1 should be found
empirically but 1 pF–2 pF is generally adequate for compensation.
SINGLE-SUPPLY APPLICATIONS
Current Mode Operation
Figure 6 shows a typical circuit for operation with a single 2.5 V
to 5 V supply. In the current mode circuit of Figure 6, I
OUT
2
and hence I
OUT
1 is biased positive by an amount applied to
V
BIAS
. In this configuration, the output voltage is given by
×
(
V
D
R
/R
V
V
V
OUT
FB
DAC
BIAS –
IN
BIAS
=
)
×
(
)
{
}
+
As D varies from 0 to 255, the output voltage varies from
=
V
V
toV
V
–V
OUT
BIAS
OUT
BIAS
IN
=
2
V
OUT
V
DD
GND
V
IN
I
OUT
2
I
OUT
1
R
FB
V
DD
V
REF
V
BIAS
C1
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
A1
Figure 6. Single-Supply Current Mode Operation
V
BIAS
should be a low impedance source capable of sinking and
sourcing all possible variations in current at the I
OUT
2 terminal
without any problems.
It is important to note that V
IN
is limited to low voltages because
the switches in the DAC ladder no longer have the same source-
drain drive voltage. As a result their on resistance differs and this
degrades the linearity of the DAC.
V
OUT
=
–V
REF
to +V
REF
SCLK SDIN
GND
V
REF
10V
SYNC
I
OUT
2
I
OUT
1
V
DD
V
REF
NOTES
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V
= 0 V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
3. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED IF A1/A2 IS
A HIGH SPEED AMPLIFIER.
AGND
R3
10k
AD5425
MICROCONTROLLER
R5
20k
R4
10k
A2
R1
V
DD
R
FB
R2
C1
A1
Figure 5. Bipolar Operation (4-Quadrant Multiplication)
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