參數(shù)資料
型號: AD5422BREZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 6/44頁
文件大?。?/td> 0K
描述: IC DAC 16BIT 1CH SRL INP 24TSSOP
產(chǎn)品培訓模塊: Power Line Monitoring
Data Converter Fundamentals
DAC Architectures
設計資源: 16-Bit Fully Isolated Output Module Using AD5422 and ADuM1401 (CN0065)
Simplified 16-Bit Voltage Output and 4 mA-to-20 mA Output Solution Using AD5422 (CN0077)
標準包裝: 2,500
設置時間: 25µs
位數(shù): 16
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 950mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應商設備封裝: 24-TSSOP 裸露焊盤
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極;1 電壓,單極;1 電壓,雙極
采樣率(每秒): 40k
AD5412/AD5422
Data Sheet
Rev. I | Page 14 of 44
TYPICAL PERFORMANCE CHARACTERISTICS
GENERAL
0
100
200
300
400
500
600
700
800
900
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
D
I CC
(
A
)
LOGIC VOLTAGE (V)
DVCC = 5V
TA = 25°C
DVCC = 3V
06996-
022
Figure 7. DICC vs. Logic Input Voltage
–2
–1
0
1
2
3
4
5
10
12
14
16
18
20
22
24
26
28
AI
DD
/AI
SS
(
mA)
AVDD/|AVSS| (V)
AIDD
AISS
TA = 25°C
VOUT = 0V
OUTPUT UNLOADED
06996-
108
Figure 8. AIDD/AISS vs. AVDD/|AVSS|
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
15
20
25
30
35
40
A
I DD
(m
A
)
AVDD (V)
TA = 25°C
IOUT = 0mA
06996-
023
Figure 9. AIDD vs. AVDD
0
1
2
3
4
5
6
7
8
9
–21
–19
–17
–15
–13
–11
–9
–7
–5
–3
–1
1
D
V
C
OU
T
PU
T
V
O
L
T
A
G
E
(V)
LOAD CURRENT (mA)
TA = 25°C
06996-
024
Figure 10. DVCC Output Voltage vs. Load Current
CH1 2.00V
CH3 5.00V
M200s
CH3
2.1V
1
3
AVDD
REFERENCE OUTPUT
06996-
025
Figure 11. REFOUT Turn-on Transient
CH1 2V
M2.00s
LINE
1.8V
1
06996-
026
Figure 12. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)
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