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參數(shù)資料
| 型號： | AD5421BREZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/36頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 1.8-12V 28TSSOP |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 50µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 625mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.173"，4.40mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
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AD5421
Data Sheet
Rev. G | Page 28 of 36
CONTROL REGISTER
The control register is a read/write register and is addressed as described in Table 12. The data programmed to the control register
determines the mode of operation of the AD5421.
Table 17. Control Register Bit Map
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SPI watchdog timeout
SPI
watchdog
timer
Auto fault
readback
Alarm on
SPI fault
Set min
loop
current
Select
ADC
input
On-chip
ADC
Power down
internal
reference
VLOOP
fault
alert
Reserved
T0
T1
T2
Table 18. Control Register Bit Descriptions
Control Bits
Description
SPI watchdog
timeout
The T0, T1, and T2 bits allow the user to program the watchdog timeout period. The watchdog timer is reset when a valid
write to any AD5421 register occurs or when a NOP command is written.
T0
T1
T2
Timeout Period
0
50 ms
0
1
100 ms
0
1
0
500 ms
0
1
1 sec (default)
1
0
2 sec
1
0
1
3 sec
1
0
4 sec
1
5 sec
SPI watchdog
timer
0 = SPI watchdog timer is enabled (default).
1 = SPI watchdog timer is disabled.
Auto fault
readback
This bit specifies whether the fault register contents are automatically clocked out on the SDO pin on each write operation.
(The fault register can always be addressed for readback.)
0 = fault register contents are clocked out on the SDO pin (default).
1 = fault register contents are not clocked out on the SDO pin.
Alarm on SPI
fault
This bit specifies whether the loop current is forced to the alarm value when an SPI fault is detected (that is, the watchdog
timer times out). When an SPI fault is detected, the SPI fault bit of the fault register and the FAULT pin are always set.
0 = loop current is forced to the alarm value when an SPI fault is detected (default).
1 = loop current is not forced to the alarm value when an SPI fault is detected.
Set min loop
current
0 = normal operation (default).
1 = loop current is set to its minimum value so that the total current flowing in the loop consists only of the operating
current of the AD5421 and its associated circuitry.
Select ADC
input
0 = on-chip ADC measures the voltage between the VLOOP and COM pins (default).
1 = on-chip ADC measures the temperature of the AD5421 die.
On-chip ADC
0 = on-chip ADC is disabled (default).
1 = on-chip ADC is enabled.
Power down
internal
reference
0 = internal voltage reference is powered up (default).
1 = internal voltage reference is powered down and an external voltage reference source is required.
VLOOP fault
alert
This bit specifies whether the FAULT pin is set when the voltage between the VLOOP and COM pins falls to approximately 0.3 V.
(The VLOOP 6V bit of the fault register is always set.)
0 = FAULT pin is not set when the VLOOP COM voltage falls to approximately 0.3 V.
1 = FAULT pin is set when the VLOOP COM voltage falls to approximately 0.3 V.
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