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| 型號： | AD5398BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT CURRENT-SINK 8LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 250µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 8-LFCSP-VD（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電流，單極 |
| 采樣率（每秒）： | 31k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
| 其它名稱： | AD5398BCPZ-REEL7DKR |
AD5398
Rev. B | Page 11 of 16
THEORY OF OPERATION
The AD5398 is a fully integrated 10-bit DAC with 120 mA
output current sink capability and is intended for driving voice
coil actuators in applications such as lens autofocus, image sta-
bilization, and optical zoom. The circuit diagram is shown in
Figure 17. A 10-bit current output DAC coupled with Resistor R
generates the voltage that drives the noninverting input of the
operational amplifier. This voltage also appears across the RSENSE
resistor and generates the sink current required to drive the
voice coil.
Resistors R and RSENSE are interleaved and matched. Therefore,
the temperature coefficient and any nonlinearities over tem-
perature are matched and the output drift over temperature is
minimized. Diode D1 is an output protection diode.
05034-015
POWER-ON
RESET
3
SDA
7
AGND
2
DGND
6
VDD
4
SCL
1
PD
8
ISINK
VBAT
VOICE
COIL
ACTUATOR
D1
RSENSE
3.3
Ω
I2C SERIAL
INTERFACE
10-BIT
CURRENT
OUTPUT DAC
REFERENCE
R
AD5398
5
DGND
Figure 17. Block Diagram Showing Connection to Voice Coil
SERIAL INTERFACE
The AD5398 is controlled using the industry-standard I2C
2-wire serial protocol. Data can be written to or read from the
DAC at data rates up to 400 kHz. After a read operation, the
contents of the input register are reset to all zeros.
I2C BUS OPERATION
An I2C bus operates with one or more master devices that
generate the serial clock (SCL), and read/write data on the serial
data line (SDA) to/from slave devices such as the AD5398. All
devices on an I2C bus have their SCL pin connected to the SDA
line and their SCL pin connected to the SCL line. I2C devices
can only pull the bus lines low; pulling high is achieved by pull-
up resistors RP. The value of RP depends on the data rate, bus
capacitance, and the maximum load current that the I2C device
can sink (3 mA for a standard device).
05034-016
SCL
SDA
I2C MASTER
DEVICE
AD5398
I2C SLAVE
DEVICE
I2C SLAVE
DEVICE
RP
VDD
Figure 18. Typical I2C Bus
When the bus is idle, SCL and SDA are both high. The master
device initiates a serial bus operation by generating a start
condition, which is defined as a high-to-low transition on the
SDA low while SCL is high. The slave device connected to the
bus responds to the start condition and shifts in the next eight
data bits under control of the serial clock. These eight data bits
consist of a 7-bit address, plus a read/write bit, which is 0 if data
is to be written to a device, and 1 if data is to be read from a
device. Each slave device on an I2C bus must have a unique
address. The address of the AD5398 is 0001100; however,
0001101, 0001110, and 0001111 address the part because the
last two bits are unused/don’t care (see Figure 19 and Figure 20).
Since the address plus R/W bit always equals eight bits of data,
another way of looking at it is that the write address of the
AD5398 is 0001 1000 (0x18) and the read address is 0001 1001
(0x19). Again, Bit 6 and Bit 7 of the address are unused, and
therefore the write addresses can also be 0x1A, 0x1C, and 0x1E,
and the read address can be 0x1B, 0x1D, and 0x1F (see Figure 19
and Figure 20).
At the end of the address data, after the R/W bit, the slave
device that recognizes its own address responds by generating
an acknowledge (ACK) condition. This is defined as the slave
device pulling SDA low while SCL is low before the ninth clock
pulse, and keeping it low during the ninth clock pulse. Upon
receiving ACK, the master device can clock data into the
AD5398 in a write operation, or it can clock it out in a read
operation. Data must change either during the low period of the
clock, because SDA transitions during the high period define a
start condition as described previously, or during a stop
condition as described in the Data Format section.
I2C data is divided into blocks of eight bits, and the slave
generates an ACK at the end of each block. Since the AD5398
requires 10 bits of data, two data-words must be written to it
when a write operation occurs, or read from it when a read
operation occurs. At the end of a read or write operation, the
AD5398 acknowledges the second data byte. The master
generates a stop condition, defined as a low-to-high transition
on SDA while SCL is high, to end the transaction.
DATA FORMAT
Data is written to the AD5398 high byte first, MSB first, and is
shifted into the 16-bit input register. After all data is shifted in,
data from the input register is transferred to the DAC register.
Because the DAC requires only 10 bits of data, not all bits of the
input register data are used. The MSB is reserved for an active-
high, software-controlled, power-down function. Bit 14 is
unused; Bit 13 to Bit 4 correspond to the DAC data bits, Bit 9 to
Bit 0. Bit 3 to Bit 0 are unused.
During a read operation, data is read in the same bit order.
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