參數(shù)資料
型號(hào)： AD5392BSTZ-3
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 31/44頁(yè)
文件大小： 0K
描述： IC DAC 14BIT 8CHAN 3V 52LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5390/1/2 Redesign Change 16/May/2012
設(shè)計(jì)資源： 8 to 16 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5390/1/2 (CN0029)
AD5390/91/92 Channel Monitor Function (CN0030)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 8µs
位數(shù)： 14
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 16
電壓電源： 單電源
功率耗散（最大）： 35mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 52-LQFP
供應(yīng)商設(shè)備封裝： 52-LQFP（10x10）
包裝： 托盤(pán)
輸出數(shù)目和類(lèi)型： 8 電壓，單極
采樣率（每秒）： 125k
Data Sheet
AD5390/AD5391/AD5392
Rev. E | Page 37 of 44
APPLICATION INFORMATION
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD539x is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD539x is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
For supplies with multiple pins (AVDD, AVCC), it is recom-
mended to tie those pins together. The AD539x should have
ample supply bypassing of 10 F in parallel with 0.1 F on each
supply located as close to the package as possible—ideally right
up against the device. The 10 F capacitors are the tantalum
bead type. The 0.1 F capacitor should have low effective series
resistance (ESR) and effective series inductance (ESI), such as
the common ceramic types that provide a low impedance path
to ground at high frequencies, to handle transient currents due
to internal logic switching.
The power supply lines of the AD539x should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never run near the reference inputs. A ground line routed
between the DIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board, because
there is a separate ground plane, but separating the lines helps).
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A micro-strip technique is by far the best, but not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground plane,
while signal traces are placed on the soldered side.
TYPICAL CONFIGURATION CIRCUIT
Figure 41 shows a typical configuration for the AD539x when
configured for use with an external reference. In the circuit
shown, all AGND, SIGNAL_GND, and DAC_GND pins are
tied together to a common AGND. AGND and DGND are
connected together at the AD539x device. On power-up,
the AD539x defaults to external reference operation. All
AVDD lines are connected together and driven from the same
5 V source. It is recommended to decouple close to the device
with a 0.1 F ceramic and a 10 F tantalum capacitor. In this
application, the reference for the AD539x-5 is provided
externally from either an ADR421 or ADR431 2.5 V reference.
Suitable external references for the AD539x-3 include the
ADR280 1.2 V reference. The reference should be decoupled at
the REFOUT/REFIN pin of the device with a 0.1 F capacitor.
03773-
061
ADR431/
ADR421
AD539x
AVDD
DVDD
SIGNAL_GND
DAC_GND
DGND
VOUT 15
VOUT 0
AGND
REFOUT/REFIN
REF_GND
0.1F
10F
0.1F
AVDD
DVDD
Figure 41. Typical Configuration with External Reference
Figure 42 shows a typical configuration when using the internal
reference. On power-up, the AD539x defaults to an external
reference; therefore, the internal reference needs to be configured
and turned on via a write to the AD539x control register. On the
AD5390/AD5392, Control Register Bit CR12 lets the user choose
the reference voltage; Bit CR10 is used to select the internal
reference. It is recommended to use the 2.5 V reference when
AVDD = 5 V, and the 1.25 V reference when AVDD = 3 V. On the
AD5391, Control Register Bit CR10 lets the user choose the ref-
erence voltage; Bit CR8 is used to select the internal reference.
03773-
060
AD539x
AVDD
DVDD
SIGNAL_GND
DAC_GND
DGND
VOUT 15
VOUT 0
AGND
REFOUT/REFIN
REF_GND
0.1F
10F
0.1F
AVDD
DVDD
Figure 42. Typical Configuration with Internal Reference.
(Digital Connections Omitted for Clarity)
The AD539x contains an internal power-on reset circuit with a
10 ms brown-out time. If the power supply ramp rate exceeds
10 ms, the user should reset the AD539x as part of the initiali-
zation process to ensure the calibration data is loaded correctly
into the device.
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