參數(shù)資料
型號： AD5392BST-3-REEL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP52
封裝： 10 X 10 MM, MS-026BCC, LQFP-52
文件頁數(shù)： 28/44頁
文件大小： 1319K
代理商： AD5392BST-3-REEL
AD5390/AD5391/AD5392
I
2
C WRITE OPERATION
There are three specific modes in which data can be written to
the AD539x family of DACs.
Rev. A | Page 28 of 44
4-BYTE MODE
When writing to the AD539x DACs, begin with an address byte
(R/W = 0), after which the DAC acknowledges that it is pre-
pared to receive data by pulling SDA low. The address byte is
followed by the pointer byte; this addresses the specific channel
in the DAC to be addressed and is also acknowledged by the
DAC. Address Bits A3 to A0 address all channels on the
AD5390/AD5391. Address Bits A2 to A0 address all channels on
the AD5392. Address Bit A3 is a zero on the AD5392. Two bytes
of data then are written to the DAC, as shown in Figure 33. A
STOP condition follows. This lets the user update a single
channel within the AD539x at any time and requires four bytes
of data to be transferred from the master.
REG0
MSB
MSB
LSB
LSB
REG1
1
0
0
0
0
0
0
A3
A2
A1
A0
1
1
AD1
AD0
R/W
0
SCL
SDA
SCL
SDA
START
CONDITION
BY
MASTER
ACK
BY
CONVERTER
ACK
BY
CONVERTER
ADDRESS BYTE
POINTER BYTE
MSB
ACK
BY
CONVERTER
ACK
BY
CONVERTER
STOP
CONDITION
BY
MASTER
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
Figure 33. The 4-Byte Mode I
2
C Write Operation
相關(guān)PDF資料
PDF描述
AD539J Quad 12-bit 125MSPS ADC with serialized LVDS output 64-VQFN -40 to 85
AD539K Quad 12-bit 125MSPS ADC with serialized LVDS output 64-VQFN -40 to 85
AD539KD Wideband Dual-Channel Linear Multiplier/Divider
AD539S Wideband Dual-Channel Linear Multiplier/Divider
AD539SD Wideband Dual-Channel Linear Multiplier/Divider
相關(guān)代理商/技術(shù)參數(shù)
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