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參數(shù)資料
| 型號： | AD5391BCP-3-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| 中文描述： | SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, QCC64 |
| 封裝： | 9 X 9 MM, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 13/44頁 |
| 文件大?。?/td> | 1319K |
| 代理商： | AD5391BCP-3-REEL |
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AD5390/AD5391/AD5392
TIMING CHARACTERISTICS: I
2
C SERIAL INTERFACE
Guaranteed by design and characterization, not production tested. DV
DD
= 2.7 V to 5.5 V; AV
DD
= 2.7 V to 5.5 V; AGND = DGND = 0 V.
All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 7.
Parameter
1
Limit at T
MIN
, T
MAX
Unit
Description
F
SCL
400
kHz max
SCL clock frequency
t
1
2.5
μs min
SCL cycle time
t
2
0.6
μs min
t
HIGH
, SCL high time
t
3
1.3
μs min
t
LOW
, SCL low time
t
4
0.6
μs min
t
HD
,
STA
, start/repeated start condition hold time
t
5
100
ns min
t
SU
,
DAT
, data setup time
t
62
0.9
μs max
t
HD
,
DAT
data hold time
0
μs min
t
HD
,
DAT
data hold time
t
7
0.6
μs min
t
SU
,
STA
setup time for repeated start
t
8
0.6
μs min
t
SU
,
STO
stop condition setup time
t
9
1.3
μs min
t
BUF
, bus free time between a stop and a start condition
t
10
300
ns max
t
F
, fall time of SDA when transmitting
0
ns min
t
R
, rise time of SCL and SDA when receiving (CMOS-compatible)
t
11
300
ns max
t
F
, fall time of SDA when transmitting
0
ns min
t
F
, fall time of SDA when receiving (CMOS-compatible)
300
ns max
t
F
, fall time of SCL and SDA when receiving
20 + 0.1 C
B
ns min
t
F
, fall time of SCL and SDA when transmitting
C
B3
400
pF max
Capacitive load for each bus line
Rev. A | Page 13 of 44
1
See F
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
MIN of the SCL signal)
to bridge the undefined region of SCL’s falling edge.
3
C
B
is the total capacitance of one bus line in pF; t
R
and t
F
measured between 0.3 DV
DD
and 0.7 DV
DD
.
.
igure 6
0
SCL
SDA
START
CONDITION
RSTART
CONDITION
CSTOP
t
9
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
8
t
1
Figure 6. I
2
C Interface Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD5391BST-3 | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| AD5391BST-5 | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| AD5391BST-5-REEL | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| AD5392 | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| AD5392BST-3 | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
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|---|---|
| AD5391BCP-3-REEL7 | 制造商:Analog Devices 功能描述:DAC 16-CH Resistor-String 12-bit 64-Pin LFCSP EP T/R |
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| AD5391BCP-5-REEL | 制造商:Analog Devices 功能描述:DAC 16-CH Resistor-String 12-bit 64-Pin LFCSP EP T/R |
| AD5391BCP-5-REEL7 | 制造商:Analog Devices 功能描述:DAC 16-CH Resistor-String 12-bit 64-Pin LFCSP EP T/R |
| AD5391BCPZ-3 | 功能描述:IC DAC 12BIT I2C 16CH 3V 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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