參數(shù)資料
型號： AD5390BST-5-REEL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP52
封裝： 10 X 10 MM, MS-026BCC, LQFP-52
文件頁數(shù)： 13/44頁
文件大小： 1319K
代理商： AD5390BST-5-REEL
AD5390/AD5391/AD5392
TIMING CHARACTERISTICS: I
2
C SERIAL INTERFACE
Guaranteed by design and characterization, not production tested. DV
DD
= 2.7 V to 5.5 V; AV
DD
= 2.7 V to 5.5 V; AGND = DGND = 0 V.
All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 7.
Parameter
1
Limit at T
MIN
, T
MAX
Unit
Description
F
SCL
400
kHz max
SCL clock frequency
t
1
2.5
μs min
SCL cycle time
t
2
0.6
μs min
t
HIGH
, SCL high time
t
3
1.3
μs min
t
LOW
, SCL low time
t
4
0.6
μs min
t
HD
,
STA
, start/repeated start condition hold time
t
5
100
ns min
t
SU
,
DAT
, data setup time
t
62
0.9
μs max
t
HD
,
DAT
data hold time
0
μs min
t
HD
,
DAT
data hold time
t
7
0.6
μs min
t
SU
,
STA
setup time for repeated start
t
8
0.6
μs min
t
SU
,
STO
stop condition setup time
t
9
1.3
μs min
t
BUF
, bus free time between a stop and a start condition
t
10
300
ns max
t
F
, fall time of SDA when transmitting
0
ns min
t
R
, rise time of SCL and SDA when receiving (CMOS-compatible)
t
11
300
ns max
t
F
, fall time of SDA when transmitting
0
ns min
t
F
, fall time of SDA when receiving (CMOS-compatible)
300
ns max
t
F
, fall time of SCL and SDA when receiving
20 + 0.1 C
B
ns min
t
F
, fall time of SCL and SDA when transmitting
C
B3
400
pF max
Capacitive load for each bus line
Rev. A | Page 13 of 44
1
See F
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
MIN of the SCL signal)
to bridge the undefined region of SCL’s falling edge.
3
C
B
is the total capacitance of one bus line in pF; t
R
and t
F
measured between 0.3 DV
DD
and 0.7 DV
DD
.
.
igure 6
0
SCL
SDA
START
CONDITION
RSTART
CONDITION
CSTOP
t
9
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
8
t
1
Figure 6. I
2
C Interface Timing Diagram
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