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參數(shù)資料
| 型號(hào)： | AD538AD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Real-Time Analog Computational Unit ACU |
| 中文描述： | ANALOG MULTIPLE FUNCTIONS, 0.4 MHz BAND WIDTH, CDIP18 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-18 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 167K |
| 代理商： | AD538AD |
AD538
–8–
REV. C
LOG RATIO OPERATION
Figure 14 shows the AD538 configured for computing the log of
the ratio of two input voltages (or currents). The output signal
from B is connected to the summing junction of the output ampli-
fier via two series resistors. The 90.9
metal film resistor effec-
tively degrades the temperature coefficient of the
±
3500 ppm/
°
C
resistor to produce a 1.09 k
+3300 ppm/
°
C equivalent value.
In this configuration, the V
Y
input must be tied to some voltage
less than zero (–1.2 V in this case) removing this input from the
transfer function.
The 5 k
potentiometer controls the circuit’s scale factor ad-
justment providing a +1 V per decade adjustment. The output
offset potentiometer should be set to provide a zero output with
V
X
= V
Z
= 1 V. The input V
Z
adjustment should be set for an
output of 3 V with V
Z
= l mV and V
X
= 1 V.
25k
V
25k
V
LOG
RATIO
100
V
25k
V
25k
V
ANTILOG
LOG
OUTPUT
100
V
AD538
INTERNAL
VOLTAGE
REFERENCE
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
I
V
O
I
Z
V
Z
B
+10V
+2V
I
Y
A
D
I
X
V
X
C
PWR
GND
SIGNAL
GND
V
Y
+15V
–15V
IN4148
V
O
= 1V LOG
10
( )
V
Z
X
OUTPUT
2k
V
1%
5k
V
SCALE
FACTOR
ADJUST
AD589
–1.2V
–V
S
OPTIONAL
INPUT V
ADJUSTMENT
V
INPUT
1M
V
10M
V
90.9
V
1%
1k
+3500
ppm/
8
C
+V
S
–V
S
10M
V
10k
V
OPTIONAL
OUTPUT V
ADJUSTMENT
68k
V
5%
48.7
V
Figure 14. Log Ratio Circuit
The log ratio circuit shown achieves
±
0.5% accuracy in the log
domain for input voltages within three decades of input range:
10 mV to 10 V. This error is not defined as a percent of full-
scale output, but as a percent of input. For example, using a
1 V/decade scale factor, a 1% error in the positive direction at
the INPUT of the log ratio amplifier translates into a 4.3 mV
deviation from the ideal OUTPUT (i.e., 1 V
×
log
10
(1.01) =
4.3214 mV). An input error 1% in the negative direction is
slightly different, giving an output deviation of 4.3648 mV.
TWO-QUADRANT DIVISION
The two-quadrant linear divider circuit illustrated in Figure 13
uses the same basic connections as the one-quadrant version.
However, in this circuit the numerator has been offset in the
positive direction by adding the denominator input voltage to it.
The offsetting scheme changes the divider’s transfer function
from:
V
O
=
10
V
V
Z
V
X
to:
V
O
=
10
V
V
Z
+
AV
X
(
V
X
)
=
10
V
1
A
+
V
Z
V
X
=
10
A
+
10
V
V
Z
V
X
where
A
=
35
k
25
k
As long as the magnitude of the denominator input is equal to
or greater than the magnitude of the numerator input, the cir-
cuit will accept bipolar numerator voltages. However, under the
conditions of a 0 V numerator input, the output would incor-
rectly equal +14 V. The offset can be removed by connecting
the +10 V reference through resistors R1 and R2 to the output
section’s summing node I at Pin 9 thus providing a gain of 1.4
at the center of the trimming potentiometer. The pot R2 adjusts
out or corrects this offset, leaving the desired transfer function
of 10 V (V
Z
/V
X
).
25k
V
25k
V
LOG
RATIO
100
V
25k
V
25k
V
ANTILOG
LOG
OUTPUT
100
V
AD538
INTERNAL
VOLTAGE
REFERENCE
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
I
V
O
I
Z
V
Z
B
+10V
+2V
I
Y
A
D
I
X
V
SIGNAL
GND
C
PWR
GND
V
Y
+15V
–15V
IN4148
V
OUT
= 10
(
)
V
Z
V
X
FOR
V
X
$
V
Z
OUTPUT
R1
12.4k
V
R2
10k
V
ZERO
ADJUST
AD589
1M
V
V
OS
ADJ
68k
V
5%
–1.2V
3.9M
V
35k
V
NUMERATOR
V
Z
10M
V
–V
S
OPTIONAL
Z OFFSET TRIM
DENOMINATOR
V
X
35k
V
Figure 13. Two-Quadrant Division with 10 V Scaling
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD538BD | Real-Time Analog Computational Unit ACU |
| AD538SD | Real-Time Analog Computational Unit ACU |
| AD538ACHIPS | Real-Time Analog Computational Unit ACU |
| AD539 | AD539: Wideband Dual-Channel Linear Multiplier/Divider Data Sheet (Rev. A. 12/91) |
| AD539KN | Wideband Dual-Channel Linear Multiplier/Divider |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD538ADZ | 功能描述:IC REALTIME ACU UNIT 18-CDIP RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD538BD | 功能描述:IC MULT/DIV REALTIME ACU 18-CDIP RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD538BDZ | 功能描述:IC MULT/DIV REALTIME ACU 18-CDIP RoHS:是 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD538SD | 功能描述:IC MULT/DIV REALTIME ACU 18-CDIP RoHS:否 類別:集成電路 (IC) >> 線性 - 模擬乘法器，除法器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:HA 功能:模擬乘法器 位元/級(jí)數(shù):四象限 封裝/外殼:16-CDIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-CDIP 側(cè)面銅焊 包裝:管件 |
| AD538SD/883B | 功能描述:增效器/分頻器 MULT/DIV ACU IC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Multiplier 邏輯系列: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-14 |
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