參數(shù)資料
型號: AD5383BSTZ-5
廠商: Analog Devices Inc
文件頁數(shù): 23/40頁
文件大?。?/td> 0K
描述: IC DAC 12BIT 32CH 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: AD5381,3 Redesign Change 24/Oct/2011
設(shè)計資源: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5383 (CN0014)
AD5383 Channel Monitor Function (CN0015)
標(biāo)準(zhǔn)包裝: 1
設(shè)置時間: 6µs
位數(shù): 12
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 32
電壓電源: 單電源
功率耗散(最大): 65mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
輸出數(shù)目和類型: 32 電壓,單極;32 電壓,雙極
采樣率(每秒): 167k
Data Sheet
AD5383
Rev. C | Page 3 of 40
GENERAL DESCRIPTION
The AD5383 is a complete, single-supply, 32-channel, 12-bit
denseDAC available in a 100-lead LQFP package. All 32
channels have an on-chip output amplifier with rail-to-rail
operation. The AD5383 includes a programmable internal 1.25
V/2.5 V, 10 ppm/°C reference; an on-chip channel monitor
function that multiplexes the analog outputs to a common
MON_OUT pin for external monitoring; and an output
amplifier boost mode that allows optimization of the amplifier
slew rate. The AD5383 features
Double-buffered parallel interface with a 20 ns WR pulse
width.
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial
interface with interface speeds in excess of 30 MHz.
I2C-compatible interface that supports a 400 kHz data
transfer rate.
An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated indepen-
dently or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjust
register that allows the user to fully calibrate any DAC channel.
With boost off, power consumption is typically 0.25 mA/channel.
Table 1 and Table 2 show additional products featuring high
channel count, low voltage, single-supply operation, and bipolar
voltage output operation.
Table 1. Other High Channel Count, Low Voltage, Single-Supply DAC Products in Portfolio
Model
Resolution
AVDD Range
Output Channels
Linearity Error (LSB)
Package Description
Package Option
AD5380BSTZ-5
14 Bits
4.5 V to 5.5 V
40
±4
100-Lead LQFP
ST-100
AD5380BSTZ-3
14 Bits
2.7 V to 3.6 V
40
±4
100-Lead LQFP
ST-100
AD5381BSTZ-5
12 Bits
4.5 V to 5.5 V
40
±1
100-Lead LQFP
ST-100
AD5381BSTZ-3
12 Bits
2.7 V to 3.6 V
40
±1
100-Lead LQFP
ST-100
AD5382BSTZ-5
14 Bits
4.5 V to 5.5 V
32
±4
100-Lead LQFP
ST-100
AD5382BSTZ-3
14 Bits
2.7 V to 3.6 V
32
±4
100-Lead LQFP
ST-100
AD5390BSTZ-5
14 Bits
4.5 V to 5.5 V
16
±3
52-Lead LQFP
ST-52
AD5390BCPZ-5
14 Bits
4.5 V to 5.5 V
16
±3
64-Lead LFCSP
CP-64
AD5390BSTZ-3
14 Bits
2.7 V to 3.6 V
16
±4
52-Lead LQFP
ST-52
AD5390BCPZ-3
14 Bits
2.7 V to 3.6 V
16
±4
64-Lead LFCSP
CP-64
AD5391BSTZ-5
12 Bits
4.5 V to 5.5 V
16
±1
52-Lead LQFP
ST-52
AD5391BCPZ-5
12 Bits
4.5 V to 5.5 V
16
±1
64-Lead LFCSP
CP-64
AD5391BSTz-3
12 Bits
2.7 V to 3.6 V
16
±1
52-Lead LQFP
ST-52
AD5391BCPZ-3
12 Bits
2.7 V to 3.6 V
16
±1
64-Lead LFCSP
CP-64
AD5392BSTZ-5
14 Bits
4.5 V to 5.5 V
8
±3
52-Lead LQFP
ST-52
AD5392BCPZ-5
14 Bits
4.5 V to 5.5 V
8
±3
64-Lead LFCSP
CP-64
AD5392BSTZ-3
14 Bits
2.7 V to 3.6 V
8
±4
52-Lead LQFP
ST-52
AD5392BCPZ-3
14 Bits
2.7 V to 3.6 V
8
±4
64-Lead LFCSP
CP-64
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