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參數(shù)資料
| 型號： | AD5380BST-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100 |
| 封裝： | 14 X 14 MM, MS-026BED, LQFP-100 |
| 文件頁數(shù)： | 29/34頁 |
| 文件大?。?/td> | 975K |
| 代理商： | AD5380BST-5 |
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PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
AD5380
–29–
The AD5380 can be interfaced to a variety of 16-bit
microcontrollersor DSP processors. Figure 14 shows the
AD5380 family interfaced to a generic 16-bit
microcontroller/DSP processor. The lower address lines
from the processor are connected to A0 to A5 on the
AD5380 as shown. The upper address lines are decoded to
provide a CS,
LDAC
signals for the AD5380. The fast
interface timing of the AD5380 allows direct interface to a
wide variety of microcontrollers and DSPs as shown in
Figure 14.
AD5380 to MC68HC11
The Serial Peripheral Interface (SPI) on the MC68HC11
is configured for Master Mode (MSTR = 1), Clock Po-
larity Bit (CPOL) = 0 and the Clock Phase Bit (CPHA)
= 1. The SPI is configured by writing to the SPI Control
Register (SPCR)—see
68HC11 User Manual
. SCK of
the 68HC11 drives the SCLK of the AD5380, the MOSI
output drives the serial data line (D
IN
) of the AD5380 and
the MISO input is driven from D
OUT
. The
SYNC
signal is
derived from a port line (PC7). When data is being
transmitted to the AD5380, the
SYNC
line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle.
AD5380 to PIC16C6x/7x
The PIC16C6x/7x Synchronous Serial Port (SSP) is
configured as an SPI Master with the Clock Polarity bit =
0. This is done by writing to the Synchronous Serial Port
Control Register(SSPCON). See user
PIC16/17 Mi-
crocontroller User Manual
. In this example I/O
port RA1 is being used to pulse
SYNC
and enable the
serial port of the AD5380. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive read/write opera-
tions are needed depending on the mode. Figure 16 shows
the connection diagram.
MISO
SCK
MC68HC11
RESET
SCLK
SDO
DIN
SYNC
AD538X
DV
DD
SPI/I2C
PC7
SER/PAR
MOSI
Figure 15 . AD5380 -MC68HC11 Interface
SCK/RC3
PIC16C6X/7X
RESET
SCLK
SDO
DIN
SYNC
AD538X
DV
DD
SPI/I2C
RA1
SER/PAR
SDO/RC5
SDI/RC4
Figure 16 . AD5380 -PIC16C6X/7X Interface
RxD
TxD
8XC51
RESET
SCLK
SDO
DIN
SYNC
AD538X
DV
DD
DV
DD
SPI/I2C
P1.1
SER/PAR
Figure 17 . AD5380 - 8051 Interface
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