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| 型號(hào)： | AD537SD |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 683K |
| 描述： | IC V/F CONV 14-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 電壓至頻率 |
| 頻率 - 最大： | 100kHz |
| 全量程： | ±30ppm/°C |
| 線性： | ±0.05% |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-CDIP |
| 包裝： | 管件 |
Applying the AD537
CIRCUIT OPERATION
Block diagrams of the AD537 are shown above. A versatile
operational amplifier (BUF) serves as the input stage; its pur-
pose is to convert and scale the input voltage signal to a drive
current in the NPN follower. Optimum performance is achieved
when, at the full-scale input voltage, a 1mA drive current is
delivered to the current-to-frequency converter. The drive cur-
rent to the current-to-frequency converter (an astable
multivibrator) provides both the bias levels and the charging
current to the externally connected timing capacitor. This
adaptive bias scheme allows the oscillator to provide low non-
linearity over the entire current input range of 0.1礎(chǔ) to
2000礎(chǔ). The square wave oscillator output goes to the output
driver which provides a floating base drive to the NPN power
transistor. This floating drive allows the logic interface to be ref-
erenced to a different level than V
S
. The SYNC input ( D
package only) allows the oscillator to be slaved to an external
master oscillator; this input can also be used to shut off the
oscillator.
The reference generator uses a bandgap circuit (this allows
single-supply operation to 4.5 volts which is not possible with
low T.C. Zeners) to provide the reference and bias levels for the
amplifier and oscillator stages. The reference generator also pro-
vides the precision, low T.C. 1.00 volt output and the V
TEMP
output which tracks absolute temperature at 1mV/K.
V-F CONNECTION FOR POSITIVE INPUT VOLTAGES
The positive voltage input range is from V
S
(ground in single
supply operation) to 4 volts below the positive supply. The con-
nection shown in Figure 1 provides a very high (250M&) input
impedance. The input voltage is converted to the proper drive
current at Pin 3 by selecting a scaling resistor. The full-scale
current is 1mA, so, for example a 10 volt range would require a
nominal 10k& resistor. The trim range required will depend on
capacitor tolerance. Full-scale currents other than 1mA can be
chosen, but linearity will be reduced; 2mA is the maximum
allowable drive.
As indicated by the scaling relationship in Figure 1, a 0.01礔
timing capacitor will give a 10kHz full-scale frequency, and
0.001礔 will give 100kHz with a 1mA drive current. The
maximum frequency is 150kHz. Polystyrene or NPO ceramic
capacitors are preferred for T.C. and dielectric absorption;
polycarbonate or mica are acceptable; other types will degrade
linearity. The capacitor should be wired very close to the
AD537.
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
GUARD RING
R2 R1
V
IN
10k&
10礔
OPTIONAL
INPUT
FILTER
C
RT
20k
R
OUT
f
OUT
+V
S
F
O
=
V
IN
10 (R
1
+ R
2
) C
BUF
Figure 1. Standard V-F Connection for Positive Input
Voltages
V-F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
OR CURRENT
A wide range of negative input voltages can be accommodated
with proper selection of the scaling resistor, as indicated in Fig-
ure 2. This connection, unlike the buffered positive connection,
is not high impedance since the 1mA F.S. drive current must be
supplied by the signal source. However, very large negative volt-
ages beyond the supply can be handled easily; just modify the
scaling resistors appropriately. Diode CR1 (HP50822811) is
necessary for overload and latchup protection for current or
voltage inputs.
If the input signal is a true current source, R1 and R2 are not
used. Full-scale calibration can be accomplished by connecting a
200k& pot in series with a fixed 27k& from Pin 7 to V
S
(see
calibration section, below).
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
BUF
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
V
IN
0 TO 10V
C
20k&
5k& (TYP)
f
OUT
+V
S
F
O
=
V
IN
10 (R
1
+ R
2
) C
CR1
0 TO 1mA
I
IN
R
1
R
2
F
OUT
=
I
IN
10C
Figure 2. V-F Connections for Negative Input Voltage or
Current
CALIBRATION
There are two independent adjustments: scale and offset. The
first is trimmed by adjustment of the scaling resistor R and the
second by the (optional) potentiometer connected to +V
S
and
the V
OS
pins ( D package only). Precise calibration requires the
use of an accurate voltage standard set to the desired FS value
and a frequency meter; a scope is useful for monitoring output
waveshape. Verification of linearity requires the availability of a
switchable voltage source (or a DAC) having a linearity error
below ?.005%, and the use of long measurement intervals to
minimize count uncertainties. Every AD537 is automatically tested
for linearity, and it will not usually be necessary to perform this
verification, which is both tedious and time-consuming.
Although drifts are small it is good practice to allow the operat-
ing environment to attain stable temperature and to ensure that
the supply, source and load conditions are proper. Begin by set-
ting the input voltage to 1/10,000 of full scale. Adjust the offset
pot until the output frequency is 1/10,000 of full scale (for ex-
ample 1Hz for FS of 10kHz). This is most easily accomplished
using a frequency meter connected to the output. Then apply
the FS input voltage and adjust the gain pot until the desired FS
frequency is indicated. In applications where the FS input is
small, this adjustment will very slightly affect the offset voltage,
due to the input bias current of the buffer amplifier. A change of
lk& in R will affect the input by approximately 100礦, which is
as much as 0.1% of a 100mV FS range. Therefore, it may be
necessary to repeat the offset and scale adjustments for the high-
est accuracy. The design of the input amplifier is such that the
input voltage drift after offset nulling is typically below l礦/癈.
REV. C
3
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