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| 型號(hào)： | AD537 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Voltage-to-Frequency Converter IC(壓頻轉(zhuǎn)換器芯片) |
| 中文描述： | 電壓頻率轉(zhuǎn)換器集成電路（壓頻轉(zhuǎn)換器芯片） |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 179K |
| 代理商： | AD537 |
AD537
REV. C
–
5
–
NONLINEARITY SPECIFICATION
The preferred method for specifying linearity error is in terms of
the maximum deviation from the ideal relationship after cali-
brating the converter at full scale and
“
zero
”
. This error will
vary with the full-scale frequency and the mode of operation.
The AD537 operates best at a 10 kHz full-scale frequency with
a negative voltage input; the linearity is typically within
±
0.05%.
Operating at higher frequencies or with positive inputs will
degrade the linearity as indicates in the Specification table. The
shape of a typical linearity plot is given in Figure 4.
0.18
0.16
0.04
0.10
0.06
10
0.08
1
0.12
0.14
10k
1k
100
OUTPUT FREQUENCY
–
Hz
N
–
–
0.08
–
0.02
–
0.06
–
0.04
0
0.02
AD537J
AD537K, S
TEST CONDITIONS:
+V
S
= +15V
–
V
= 0V
C
T
= 0.01μF
R
T
= 10k
V
=
±
10V
POS INPUT
–
FIG. 3
NEG INPUT
–
FIG. 4
Figure 4a. Typical Nonlinearity Error Envelopes with
10 kHz F.S. Output
0.18
0.16
0.04
0.10
0.06
100
0.08
10
0.12
0.14
100k
10k
1k
OUTPUT FREQUENCY
–
Hz
N
–
–
0.08
–
0.02
–
0.06
–
0.04
0
0.02
AD537J
AD537K, S
TEST CONDITIONS:
+V
S
= +15V
–
V
= 0V
C
T
= 0.001μF
R
T
= 10k
V
=
±
10V
POS INPUT
–
FIG. 3
NEG INPUT
–
FIG. 4
Figure 4b. Typical Nonlinearity Error with 100 kHz F.S.
Output
OUTPUT INTERFACING CONSIDERATIONS
The design of the output stage allows easy interfacing to all digi-
tal logic families. The collector and emitter of the output NPN
transistor are both uncommitted; the emitter can be tied to any
voltage between
–
V
S
and 4 volts below +V
S
. The open collector
can be pulled up to a voltage 36 volts above the emitter regard-
less of +V
S
. The high power output stage can supply up to
20 mA (10 mA for
“
H
”
package) at a maximum saturation volt-
age of 0.4 volts. The stage limits the output current at 25mA; it
can handle this limit indefinitely without damaging the device.
Figure 5 shows the AD537 with a standard 0 to +10 volt input
connection and the output stage connections. The values for the
logic common voltage, pull-up resistor, positive logic level, and
–
V
S
supply are given in the accompanying chart for several logic
forms.
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
C
f
OUT
LOGIC V
CC
+V
(+15V)
10k
V
IN
R
L
LOGIC COM
V
EE
V
OS
20k
–
V
S
TTL/DTL
5V CMOS
15V CMOS/
HNIL
ECL 10k
ECL2.5k
PMOS
V
CC
+5
+5
+15
0
+1.3
0
V
EE
GND
GND
GND
–
8
–
2
–
15
R
L
5k
20k
10k
5k
5k
10k
–
V
S
GND
GND
GND
–
8 TO
–
15
–
5
–
15
BUF
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
Figure 5. Interfacing Standard Logic Families
APPLICATIONS
The diagrams and descriptions of the following applications are
provided to stimulate the discerning engineer with alternative
circuit design ideas.
“
Applications of the AD537 IC Voltage-
to-Frequency Converter
”
, available from Analog Devices on
request, covers a wider range of topics and concepts in data
conversion and data transmission using voltage-to-frequency
converters.
TRUE TWO-WIRE DATA TRANSMISSION
Figure 6 shows the AD537 in a true two-wire data transmission
scheme. The twisted-pair transmission lines serves the dual pur-
pose of supplying power to the device and also carrying fre-
quency data in the form of current modulation. The PNP circuit
at the receiving end represents a fairly simple way for converting
the current modulation back into a voltage square wave which
will drive digital logic directly. The 0.6 volt square wave which
will appear on the supply line at the device terminals does not
affect the performance of the AD537 because of its excellent
supply rejection. Also, note that the circuit operates at nearly
constant average power regardless of frequency.
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
BUF
AD537
+V
IN
V
TEMP
V
REF
LOGIC
GND
+V
S
–
V
S
(CONNECTED TO CASE)
10
9
8
7
6
5
4
3
2
1
R
SCALE
R
CAL
C
TWO-WIRE
LINK
V
S
+5
+15
R
S
0
1k
R
L
1k
3.3k
120
R
S
220
+V
S
OUTPUT
R
L
V
IN
Figure 6. True Two-Wire Operation
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