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參數(shù)資料
| 型號： | AD5372BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 32CH SER 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 20µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 32 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 520mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極；32 電壓，雙極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
| 配用： | EVAL-AD5372EBZ-ND - BOARD EVAL FOR AD5372 |
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AD5372/AD5373
Rev. C | Page 20 of 28
POWER-DOWN MODE
The AD5372/AD5373 can be powered down by setting Bit 0 in
the control register to 1. This turns off the DACs, thus reducing
the current consumption. The DAC outputs are connected to
their respective SIGGNDx potentials. The power-down mode
does not change the contents of the registers, and the DACs
return to their previous voltage when the power-down bit is
cleared to 0.
THERMAL SHUTDOWN FUNCTION
The AD5372/AD5373 can be programmed to shut down the
DACs if the temperature on the die exceeds 130°C. Setting Bit 1
in the control register to 1 enables this function (see Table 16).
If the die temperature exceeds 130°C, the AD5372/AD5373 enter
a thermal shutdown mode, which is equivalent to setting the
power-down bit in the control register to 1. To indicate that the
AD5372/AD5373 have entered thermal shutdown mode, Bit 4
of the control register is set to 1. The AD5372/AD5373 remain
in thermal shutdown mode, even if the die temperature falls,
until Bit 1 in the control register is cleared to 0.
TOGGLE MODE
The AD5372/AD5373 have two X2 registers per channel, X2A
and X2B, which can be used to switch the DAC output between
two levels with ease. This approach greatly reduces the overhead
required by a microprocessor, which would otherwise need to
write to each channel individually. When the user writes to the
X1A, X1B, M, or C register, the calculation engine takes a certain
amount of time to calculate the appropriate X2A or X2B value.
If an application, such as a data generator, requires that the
DAC output switch between two levels only, any method that
reduces the amount of calculation time necessary is advanta-
geous. For the data generator example, the user needs only to
set the high and low levels for each channel once by writing to
the X1A and X1B registers. The values of X2A and X2B are
calculated and stored in their respective registers. The calculation
delay, therefore, happens only during the setup phase, that is,
when programming the initial values. To toggle a DAC output
between the two levels, it is only required to write to the relevant
A/B select register to set the MUX2 register bit. Furthermore,
because there are eight MUX2 control bits per register, it is
possible to update eight channels with a single write. Table 10
shows the bits that correspond to each DAC output.
Table 10. DACs Selected by A/B Select Registers
A/B Select
Register
F7
F6
F5
F4
F3
F2
F1
F0
0
VOUT7
VOUT6
VOUT5
VOUT4
VOUT3
VOUT2
VOUT1
VOUT0
1
VOUT15
VOUT14
VOUT13
VOUT12
VOUT11
VOUT10
VOUT9
VOUT8
2
VOUT23
VOUT22
VOUT21
VOUT20
VOUT19
VOUT18
VOUT17
VOUT16
3
VOUT31
VOUT30
VOUT29
VOUT28
VOUT27
VOUT26
VOUT25
VOUT24
1 If the bit is set to 0, Register X2A is selected. If the bit is set to 1, Register X2B is selected.
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