參數(shù)資料
型號： AD5372BSTZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 11/29頁
文件大?。?/td> 0K
描述： IC DAC 16BIT 32CH SER 64-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,500
設(shè)置時間： 20µs
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 32
電壓電源： 雙 ±
功率耗散（最大）： 520mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 32 電壓，單極；32 電壓，雙極
采樣率（每秒）： *
配用： EVAL-AD5372EBZ-ND - BOARD EVAL FOR AD5372
AD5372/AD5373
Rev. C | Page 18 of 28
The required reference levels can be calculated as follows:
1.
Identify the nominal output range on VOUT.
2.
Identify the maximum offset span and the maximum gain
required on the full output signal range.
3.
Calculate the new maximum output range on VOUT,
including the expected maximum offset and gain errors.
4.
Choose the new required VOUTMAX and VOUTMIN,
keeping the VOUT limits centered on the nominal values.
Note that VDD and VSS must provide sufficient headroom.
5.
Calculate the value of VREF as follows:
VREF = (VOUTMAX – VOUTMIN)/4
Reference Selection Example
If
Nominal output range = 12 V (4 V to +8 V)
Zero-scale error = ±70 mV
Gain error = ±3%, and
SIGGNDx = AGND = 0 V
Then
Gain error = ±3%
=> Maximum positive gain error = 3%
=> Output range including gain error = 12 + 0.03(12) = 12.36 V
Zero-scale error = ±70 mV
=> Maximum offset error span = 2(70 mV) = 0.14 V
=> Output range including gain error and zero-scale error =
12.36 V + 0.14 V = 12.5 V
VREF calculation
Actual output range = 12.5 V, that is, 4.25 V to +8.25 V;
VREF = (8.25 V + 4.25 V)/4 = 3.125 V
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
Select a convenient reference level above VREF and modify
the gain and offset registers to digitally downsize the reference.
In this way, the user can use almost any convenient reference
level but can reduce the performance by overcompaction of
the transfer function.
Use a combination of these two approaches.
CALIBRATION
The user can perform a system calibration on the AD5372/
AD5373 to reduce gain and offset errors to below 1 LSB. This
reduction is achieved by calculating new values for the M and C
registers and reprogramming them.
The M and C registers should not be programmed until both
the zero-scale and full-scale errors are calculated.
Reducing Zero-Scale Error
Zero-scale error can be reduced as follows:
1.
Set the output to the lowest possible value.
2.
Measure the actual output voltage and compare it to the
required value. This gives the zero-scale error.
3.
Calculate the number of LSBs equivalent to the error and
add this number to the default value of the C register. Note
that only negative zero-scale error can be reduced.
Reducing Full-Scale Error
Full-scale error can be reduced as follows:
1.
Measure the zero-scale error.
2.
Set the output to the highest possible value.
3.
Measure the actual output voltage and compare it to the
required value. Add this error to the zero-scale error. This
is the span error, which includes the full-scale error.
4.
Calculate the number of LSBs equivalent to the span error
and subtract this number from the default value of the M
register. Note that only positive full-scale error can be
reduced.
AD5372 Calibration Example
This example assumes that a 4 V to +8 V output is required.
The DAC output is set to 4 V but is measured at 4.03 V. This
gives a zero-scale error of 30 mV.
1 LSB = 12 V/65,536 = 183.105 μV
30 mV = 164 LSBs
The full-scale error can now be calculated. The output is set to
8 V and a value of 8.02 V is measured. This gives a full-scale
error of +20 mV and a span error of +20 mV – (–30 mV) =
+50 mV.
50 mV = 273 LSBs
The errors can now be removed as follows:
1.
Add 164 LSBs to the default C register value:
(32,768 + 164) = 32,932
2.
Subtract 273 LSBs from the default M register value:
(65,535 273) = 65,262
3.
Program the M register to 65,262; program the C register
to 32,932.
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