DVCC = 2.5 V to 5.5 V; V
參數(shù)資料
型號(hào): AD5361BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 25/29頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 16CH SERIAL 56LFCSP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 20µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 16
電壓電源: 雙 ±
功率耗散(最大): 245mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
輸出數(shù)目和類型: 16 電壓,單極;16 電壓,雙極
采樣率(每秒): *
配用: EVAL-AD5361EBZ-ND - BOARD EVAL FOR AD5361
AD5360/AD5361
Rev. A | Page 4 of 28
SPECIFICATIONS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = 16.5 V to 4.5 V; VREF = 5 V; AGND = DGND = SIGGND = 0 V; RL = open circuit;
gain (M), offset (C), and DAC offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
B Version1
Unit
Test Conditions/Comments
ACCURACY
Resolution
AD5360
16
Bits
AD5361
14
Bits
Relative Accuracy
AD5360
±4
LSB max
AD5361
±1
LSB max
Differential Nonlinearity
±1
LSB max
Guaranteed monotonic by design over temperature
Zero-Scale Error
±15
mV max
Before calibration
Full-Scale Error
±20
mV max
Before calibration
Gain Error
0.1
% FSR
Before calibration
Zero-Scale Error2
1
LSB typ
After calibration
Full-Scale Error2
1
LSB typ
After calibration
Span Error of Offset DAC
±75
mV max
See the
5
ppm FSR/°C typ
Includes linearity, offset, and gain drift
180
μV max
Typically 20 μV; measured channel at midscale, full-scale
change on any other channel
REFERENCE INPUTS (VREF0, VREF1)2
VREF Input Current
±10
μA max
Per input; typically ±30 nA
VREF Range2
2/5
V min/max
±2% for specified operation
SIGGND INPUT (SIGGND0 to SIGGND1)4
DC Input Impedance
50
kΩ min
Typically 55 kΩ
Input Range
±0.5
V max
SIGGND Gain
0.995/1.005
Min/max
OUTPUT CHARACTERISTICS2
Output Voltage Range
VSS + 1.4
V min
ILOAD = 1 mA
VDD 1.4
V max
ILOAD = 1 mA
Nominal Output Voltage Range
10 to +10
V nominal
Short-Circuit Current
15
mA max
VOUTx3 to DVCC, VDD, or VSS
Load Current
±1
mA max
Capacitive Load
2200
pF max
DC Output Impedance
0.5
Ω max
MONITOR PIN (MON_OUT)4
Output Impedance
DAC Output at Positive Full-Scale
1000
Ω typ
DAC Output at Negative Full-Scale
500
Ω typ
Three-State Leakage Current
100
nA typ
Continuous Current Limit
2
mA max
DIGITAL INPUTS
JEDEC compliant
Input High Voltage
1.7
V min
DVCC = 2.5 V to 3.6 V
2.0
V min
DVCC = 3.6 V to 5.5 V
Input Low Voltage
0.8
V max
DVCC = 2.5 V to 5.5 V
Input Current
±1
μA max
RESET, SYNC, SDI, and SCLK pins
±20
μA max
CLR, BIN/2SCOMP, and GPIO pins
Input Capacitance4
10
pF max
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