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參數(shù)資料
| 型號： | AD53500JRP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | High Speed, High Current Capability Pin Driver |
| 中文描述： | 0.4 A BUF OR INV BASED PRPHL DRVR, PDSO20 |
| 封裝： | POWER, SOIC-20 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 101K |
| 代理商： | AD53500JRP |
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD53500
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
High Speed, High Current
Capability Pin Driver
FUNCTIONAL BLOCK DIAGRAM
DRIVER
1.0
m
A/K
AD53500
V
CC
V
CC
V
EE
V
EE
V
HDCPL
V
OUT
V
LDCPL
TV
CC
THERM
GND
GND
GND
GND
GND
V
H
DATA
DATA
INH
INH
V
L
39nF
39nF
2
V
FEATURES
–2 V to +6 V Output Range
2.5
V
Output Resistance
2.5 ns Tr/Tf for a 3 V Step
300 MHz Toggle Rate
Can Drive 25
V
Lines and Lower
Peak Dynamic Current Capability of 400 mA
Inhibit Leakage <1
m
A
On-Chip Temperature Sensor
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment
PRODUCT DESCRIPTION:
The AD53500 is a complete high speed driver designed for use
in digital or mixed signal test systems where high speed and high
output drive capabilities are needed. Combining a high speed
monolithic process and a unique surface mount package, this
product attains superb electrical performance while preserving
optimum packing densities and long-term reliability thanks to an
ultrasmall 20-lead, PSOP package with built-in heat sink.
High and low reference levels can be set within a –2 V to +6 V
range with low offset voltage and high gain accuracy. A 2.5
output resistance allows use of an external backmatch resistor for
application to 50
, 25
or other complex impedance load
requirements. Without a backmatch resistor it is also capable of
driving highly capacitive loads, typically achieving a rise/fall time
of less than 10 ns with a 1000 pF capacitance. To test I/O
devices, the pin driver can be switched into a high impedance
state (Inhibit Mode), electrically removing the driver from the
path. The pin driver leakage current in inhibit is typically less
than 1
μ
A and output capacitance is typically less than 18 pF.
Transitions from HI/LO or to inhibit are controlled through the
data and inhibit inputs. The input circuitry utilizes high-speed
differential inputs with a common-mode range of –2 V to +5 V.
This allows for direct interface to the precision of differential
ECL timing or the simplicity of stimulating the pin driver from a
single-ended CMOS or TTL logic source or any combination
over the common-mode range. The analog logic HI/LO inputs
are equally easy to interface, typically requiring 50
μ
A of bias
current.
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