參數(shù)資料
型號: AD534
英文描述: 2.5 V to 5.5 V. 115 uA. Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
中文描述: 2.5伏至5.5伏115微安。并行接口單電壓輸出DAC的8-/10-/12-Bit
文件頁數(shù): 6/20頁
文件大?。?/td> 359K
代理商: AD534
REV. 0
AD5330/AD5331/AD5340/AD5341
–6–
AD5331 FUNCTIONAL BLOCK DIAGRAM
BUFFER
10-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
INTER-
FACE
LOGIC
POWER-DOWN
LOGIC
BUF
DB
9
.
DB
0
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD
GND
AD5331
RESET
POWER-ON
RESET
AD5331 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
2
3
4
5
6
7
8
9
10
11
12
DB
8
DB
9
V
REF
V
OUT
GND
CS
WR
GAIN
CLR
LDAC
PD
V
DD
Parallel Data Input.
Most Significant Bit of Parallel Data Input.
Unbuffered Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with
WR
to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with
CS
to write data to the parallel interface.
Gain Control Pin. This controls whether the output range from the DAC is 0–V
REF
or 0–2 V
REF
.
Active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
with a 10
μ
F capacitor in parallel with a 0.1
μ
F capacitor to GND.
Eight Parallel Data Inputs.
13–20
DB
0
–DB
7
AD5331 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD5331
LDAC
GAIN
WR
CS
GND
DB
8
DB
9
V
REF
V
OUT
PD
V
DD
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
10-BIT
CLR
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