參數(shù)資料
型號： AD5347BRU-REEL
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Dual 14-bit 65MSPS ADC with serialized LVDS Output 48-VQFN -40 to 85
中文描述： PARALLEL, WORD INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO38
封裝： MO-153BD-1, TSSOP-38
文件頁數(shù)： 5/24頁
文件大?。?/td> 949K
代理商： AD5347BRU-REEL
AD5346/AD5347/AD5348
TIMING CHARACTERISTICS
1, 2, 3
Table 3. V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted
Parameter
Limit at T
MIN
, T
MAX
Data Write Mode (Figure 3)
t
1
0
t
2
0
t
3
20
t
4
5
t
5
4.5
t
6
5
t
7
5
t
8
4.5
t
9
5
t
10
4.5
t
11
20
t
12
10
t
13
20
t
14
20
t
15
0
Data Readback Mode (Figure 4)
t
16
0
t
17
0
t
18
0
t
19
20
30
t
20
0
t
21
22
30
t
22
4
30
t
23
22
30
t
24
30
t
25
30
t
26
30
50
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 2.
t
1
t
2
Rev. 0 | Page 5 of 24
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
Condition/Comments
CS to WR setup time
CS to WR hold time
WR pulse width
Data, GAIN, BUF setup time
Data, GAIN, BUF hold time
Synchronous mode. WR falling to LDAC falling.
Synchronous mode. LDAC falling to WR rising.
Synchronous mode. WR rising to LDAC rising.
Asynchronous mode. LDAC rising to WR rising.
Asynchronous mode. WR rising to LDAC falling.
LDAC pulse width
CLR pulse width
Time between WR cycles
A0, A1, A2 setup time
A0, A1, A2 hold time
A0, A1, A2 to CS setup time
A0, A1, A2 to CS hold time
CS to falling edge of RD
RD pulse width; V
DD
= 3.6 V to 5.5 V
RD pulse width; V
DD
= 2.5 V to 3.6 V
CS to RD hold time
Data access time after falling edge of RD; V
DD
= 3.6 V to 5.5 V
Data access time after falling edge of RD V
DD
= 2.5 V to 3.6 V
Bus relinquish time after rising edge of RD
CS falling edge to data; V
DD
= 3.6 V to 5.5 V
CS falling edge to data; V
DD
= 2.5 V to 3.6 V
Time between RD cycles
Time from RD to WR
Time from WR to RD, V
DD
= 3.6 V to 5.5 V
Time from WR to RD, V
DD
= 2.5 V to 3.6 V
CS
WR
DATA,
GAIN, BUF
LDAC
1
LDAC
2
CLR
NOTES
1. SYNCHRONOUS LDAC UPDATE MODE
2. ASYNCHRONOUS LDAC UPDATE MODE
Figure 3. Parallel Interface Write Timing Diagram
A0–A2
t
3
t
4
t
7
t
9
t
10
t
11
t
12
t
5
t
15
t
8
t
14
t
6
t
13
0
CS
A0–A2
RD
WR
DATA
t
16
t
18
t
25
t
20
t
22
t
21
t
17
t
26
t
24
t
19
t
23
0
Figure 4. Parallel Interface Read Timing Diagram
相關PDF資料
PDF描述
AD5347BRU-REEL7 Dual 14-bit 65MSPS ADC with serialized LVDS Output 48-VQFN -40 to 85
AD5348 Dual 14-bit 65MSPS ADC with serialized LVDS Output 48-VQFN -40 to 85
AD5348BCP Dual 14-bit 65MSPS ADC with serialized LVDS Output 48-VQFN -40 to 85
AD5348BCP-REEL7 Dual 14-bit 80MSPS ADC with serialized LVDS output 48-VQFN -40 to 85
AD5348BRU Dual 14-bit 80MSPS ADC with serialized LVDS output 48-VQFN -40 to 85
相關代理商/技術參數(shù)
參數(shù)描述
AD5347BRU-REEL7 功能描述:IC DAC 10BIT OCTAL VOUT 38-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:*
AD5347BRUZ 功能描述:IC DAC 10BIT OCTAL VOUT 38TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:*
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