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參數(shù)資料
| 型號(hào)： | AD5344BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD VOUT 28-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 4.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 125k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
REV. 0
AD5334/AD5335/AD5336/AD5344
–14–
Resistor String
The resistor string section is shown in Figure 29. It is simply a
string of resistors, each of value R. The digital code loaded
to the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplier. Because it is a string of resistors, it is
guaranteed monotonic.
TO OUTPUT
AMPLIFIER
R
VREF
Figure 29. Resistor String
DAC Reference Input
The DACs operate with an external reference. The reference
inputs are unbuffered and have an input range of 0.25 V to VDD.
The impedance per DAC is typically 180 k
for 0–VREF mode
and 90 k
for 0–2 VREF mode. The AD5336 and AD5344 have
separate reference inputs for each DAC, while the AD5334 and
AD5335 have a reference inputs for each pair of DACS (A/B
and C/D).
Output Amplier
The output buffer amplier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on VREF, GAIN, the load on VOUT, and offset error.
If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V
to VREF.
If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 VREF. However because of clamping the maximum output
is limited to VDD – 0.001 V.
The output amplier is capable of driving a load of 2 k
to
GND or VDD, in parallel with 500 pF to GND or VDD. The
source and sink capabilities of the output amplier can be seen
in Figure 15.
The slew rate is 0.7 V/
s with a half-scale settling time to ±0.5 LSB
(at 8 bits) of 6
s with the output unloaded. See Figure 20.
PARALLEL INTERFACE
The AD5334, AD5336, and AD5344 load their data as a single
8-, 10-, or 12-bit word, while the AD5335 loads data as a low
byte of 8 bits and a high byte containing 2 bits.
Double-Buffered Interface
The AD5334/AD5335/AD5336/AD5344 DACs all have double-
buffered interfaces consisting of an input register and a DAC
register. DAC data and GAIN inputs (when available) are written
to the input register under control of the Chip Select (
CS) and
Write (
WR).
Access to the DAC register is controlled by the
LDAC function.
When
LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when
LDAC is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it. The gain control signal is also
double-buffered and is only updated when
LDAC is taken low.
This is useful if the user requires simultaneous updating of all
DACs and peripherals. The user may write to all input registers
individually and then, by pulsing the
LDAC input low, all out-
puts will update simultaneously.
Double-buffering is also useful where the DAC data is loaded in
two bytes, as in the AD5335, because it allows the whole data
word to be assembled in parallel before updating the DAC register.
This prevents spurious outputs that could occur if the DAC
register were updated with only the high byte or the low byte.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that
LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the input registers. In the case of the AD5334/
AD5335/AD5336/AD5344, the part will only update the DAC
register if the input register has been changed since the last
time the DAC register was updated. This removes unnecessary
crosstalk.
Clear Input (
CLR)
CLR is an active low, asynchronous clear that resets the input and
DAC registers. Note that the AD5344 has no
CLR function.
Chip Select Input (
CS)
CS is an active low input that selects the device.
Write Input (
WR)
WR is an active low input that controls writing of data to the
device. Data is latched into the input register on the rising edge
of
WR.
Load DAC Input (
LDAC)
LDAC transfers data from the input register to the DAC register
(and hence updates the outputs). Use of the
LDAC function
enables double buffering of the DAC and GAIN data. There
are two
LDAC modes:
Synchronous Mode: In this mode the DAC register is updated
after new data is read in on the rising edge of the
WR input.
LDAC can be tied permanently low or pulsed as in Figure 1.
Asynchronous Mode: In this mode the outputs are not updated
at the same time that the input register is written to. When
LDAC
goes low the DAC register is updated with the contents of the
input register.
High-Byte Enable Input (HBEN)
High-Byte Enable is a control input on the AD5335 only that
determines if data is written to the high-byte input register or
the low-byte input register.
The low data byte of the AD5335 consists of data bits 0 to 7 at
data inputs DB0 to DB7, while the high byte consists of Data
Bits 8 and 9 at data inputs DB0 and DB1. DB2 to DB7 are
ignored during a high byte write. See Figure 30.
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| AD5344BRUZ-REEL | 功能描述:IC DAC 12BIT QUAD VOUT 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AD5344BRUZ-REEL7 | 功能描述:IC DAC 12BIT QUAD VOUT 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5346 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, Parallel Interface 2.5 V to 5.5 V, Parallel Interface |
| AD5346BCP | 制造商:Analog Devices 功能描述:DAC 8-CH Resistor-String 8-bit 40-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC 8BIT DAC SERIAL I/F OCTAL 5346 |
| AD5346BCP-REEL | 制造商:Analog Devices 功能描述:DAC 8-CH Resistor-String 8-bit 40-Pin LFCSP EP T/R |
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