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參數(shù)資料
| 型號(hào)： | AD5344* |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2.5 V to 5.5 V. 500 uA. Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs |
| 中文描述： | 2.5伏至5.5伏500微安。并行接口四路電壓輸出數(shù)模轉(zhuǎn)換器8-/10-/12-Bit |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 359K |
REV. 0
AD5330/AD5331/AD5340/AD5341
–13–
I
DD
–
A
F
120
200
190
V
DD
= 5V
V
DD
= 3V
180
170
160
150
140
130
110
100
90
80
Figure 23. I
DD
Histogram with V
DD
=
3 V and V
DD
= 5 V
V
REF
–
Volts
F
–
0
2
3
4
5
0
0.2
0.4
1
V
DD
= 5V
T
A
= 25 C
–
0.2
Figure 26. Full-Scale Error vs. V
REF
250ns/DIV
0.903
0.904
0.905
0.906
0.907
0.908
0.909
0.910
0.911
0.912
0.913
0.914
0.915
0.916
0.917
Figure 24. AD5340 Major-Code Tran-
sition Glitch Energy
FREQUENCY
–
kHz
10
–
40
0.01
–
20
–
30
0
–
10
d
0.1
1
10
100
1k
10k
–
50
–
60
Figure 25. Multiplying Bandwidth
(Small-Signal Frequency Response)
FUNCTIONAL DESCRIPTION
The AD5330/AD5331/AD5340/AD5341 are single resistor-string
DACs fabricated on a CMOS process with resolutions of 8, 10,
12, and 12 bits, respectively. They are written to using a parallel
interface. They operate from single supplies of 2.5 V to 5.5 V and
the output buffer amplifiers offer rail-to-rail output swing. The
AD5330, AD5340, and AD5341 have a reference input that may
be buffered to draw virtually no current from the reference
source. The reference input of the AD5331 is unbuffered. The
devices have a power-down feature that reduces current con-
sumption to only 80 nA @ 3 V.
Digital-to-Analog Section
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the V
REF
pin provides the reference
voltage for the DAC. Figure 27 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by:
V
V
D
N
2
Gain
OUT
REF
=
×
×
where:
D
= decimal equivalent of the binary code which is loaded to the
DAC register:
0–255 for AD5330 (8 Bits)
0–1023 for AD5331 (10 Bits)
0–4095 for AD5340/AD5341 (12 Bits)
N
= DAC resolution
Gain
= Output Amplifier Gain (1 or 2)
V
OUT
GAIN
V
REF
BUF
DAC
REGISTER
INPUT
REGISTER
RESISTOR
STRING
OUTPUT
BUFFER AMPLIFIER
REFERENCE
BUFFER
Figure 27. Single DAC Channel Architecture
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