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參數(shù)資料
| 型號： | AD5341BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 359K |
| 代理商： | AD5341BRU |
REV. 0
–2–
AD5330/AD5331/AD5340/AD5341–SPECIFICATIONS
(V
DD
= 2.5 V to 5.5 V, V
REF
= 2 V. R
L
= 2 k to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
unless otherwise noted.)
B Version
2
Min
Parameter
1
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5330
Resolution
Relative Accuracy
Differential Nonlinearity
AD5331
Resolution
Relative Accuracy
Differential Nonlinearity
AD5340/AD5341
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
5
Upper Deadband
Offset Error Drift
6
Gain Error Drift
6
DC Power Supply Rejection Ratio
6
8
±
0.15
±
0.02
Bits
LSB
LSB
±
1
±
0.25
Guaranteed Monotonic By Design Over All Codes
10
±
0.5
±
0.05
Bits
LSB
LSB
±
4
±
0.5
Guaranteed Monotonic By Design Over All Codes
12
±
2
±
0.2
±
0.4
±
0.15
10
10
–12
–5
–60
Bits
LSB
LSB
% of FSR
% of FSR
mV
mV
ppm of FSR/
°
C
ppm of FSR/
°
C
dB
±
16
±
1
±
3
±
1
60
60
Guaranteed Monotonic By Design Over All Codes
Lower Deadband Exists Only if Offset Error Is Negative
V
DD
= 5 V. Upper Deadband Exists Only if V
REF =
V
DD
V
DD
=
±
10%
DAC REFERENCE INPUT
6
V
REF
Input Range
1
0.25
V
DD
V
DD
V
V
M
k
k
dB
Buffered Reference (AD5330, AD5340, and AD5341)
Unbuffered Reference
Buffered Reference (AD5330, AD5340, and AD5341)
Unbuffered Reference. Gain = 1, Input Impedance = R
DAC
Unbuffered Reference. Gain = 2, Input Impedance = R
DAC
Frequency = 10 kHz
V
REF
Input Impedance
>10
180
90
–90
Reference Feedthrough
OUTPUT CHARACTERISTICS
6
Minimum Output Voltage
4,
7
Maximum Output Voltage
4, 7
DC Output Impedance
Short Circuit Current
0.001
V
DD
–0.001
0.5
25
15
2.5
5
V min
V max
mA
mA
μ
s
μ
s
Rail-to-Rail Operation
V
DD
= 5 V
V
DD
= 3 V
Coming Out of Power-Down Mode. V
DD
= 5 V
Coming Out of Power-Down Mode. V
DD
= 3 V
Power-Up Time
LOGIC INPUTS
6
Input Current
V
IL
, Input Low Voltage
±
1
μ
A
V
V
V
V
V
V
pF
0.8
0.6
0.5
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
V
DD
= 2.5 V
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
V
DD
= 2.5 V
V
IH
, Input High Voltage
2.4
2.1
2.0
Pin Capacitance
3
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
2.5
5.5
V
DACs active and excluding load currents. Unbuffered
Reference. V
IH
= V
DD
, V
IL
= GND.
I
DD
increases by 50
μ
A at V
REF
> V
DD
– 100 mV.
In Buffered Mode extra current is (5 + V
REF
/R
DAC
)
μ
A,
where R
DAC
is the resistance of the resistor string.
140
115
250
200
μ
A
μ
A
I
DD
(Power-Down Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
0.2
0.08
1
1
μ
A
μ
A
NOTES
1
See Terminology section.
2
Temperature range: B Version: –40
°
C to +105
°
C; typical specifications are at 25
°
C.
3
Linearity is tested using a reduced code range: AD5330 (Code 8 to 255); AD5331 (Code 28 to 1023); AD5340/AD5341 (Code 115 to 4095).
4
DC specifications tested with output unloaded.
5
This corresponds to x codes. x = Deadband voltage/LSB size.
6
Guaranteed by design and characterization, not production tested.
7
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
REF
= V
DD
and
“Offset plus Gain” Error must be positive.
Specifications subject to change without notice.
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