參數(shù)資料
型號(hào): AD5340BRUZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 2/28頁(yè)
文件大?。?/td> 0K
描述: IC DAC 12BIT SNGL VOUT 24-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 8µs
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1.25mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 125k
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 10 of 28
BUFFER
12-BIT
DAC
R
EG
IST
ER
LOW BYTE
REGISTER
INT
E
RF
ACE
L
O
G
IC
POWER-DOWN
LOGIC
BUF
DB7
DB0
..
HBEN
CS
WR
CLR
LDAC
VREF
VDD
VOUT
PD
GND
AD5341
POWER-ON
RESET
9
7
6
1
13
20
2
GAIN 8
3
12
4
11
5
HIGH BYTE
REGISTER
10
06
85
2-
0
09
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
LDAC
GAIN
WR
CS
GND
VREF
VOUT
CLR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VDD
PD
TOP VIEW
(Not to Scale)
AD5341
10-BIT
HBEN
BUF
06
85
2-
010
Figure 9. AD5341 Functional Block Diagram
Figure 10. AD5341 Pin Configuration
Table 8. AD5341 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
HBEN
High Byte Enable Pin. This pin is used when writing to the device to determine if data is written to the high
byte register or the low byte register.
2
BUF
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
3
VREF
Reference Input.
4
VOUT
Output of DAC. Buffered output with rail-to-rail operation.
5
GND
Ground reference point for all circuitry on the part.
6
CS
Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
7
WR
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
8
GAIN
Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
9
CLR
Asynchronous active low control input that clears all input registers and DAC registers to zero.
10
LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
11
PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12
VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
13 to 20
DB0 to DB7
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
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