參數(shù)資料
型號(hào)： AD5340BRU
廠商： ANALOG DEVICES INC
元件分類(lèi)： DAC
英文描述： 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
中文描述： PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO24
封裝： PLASTIC, TSSOP-24
文件頁(yè)數(shù)： 1/20頁(yè)
文件大?。?/td> 359K
代理商： AD5340BRU
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD5330/AD5331/AD5340/AD5341
*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
2.5 V to 5.5 V, 115 A, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
BUFFER
8-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
INTER-
FACE
LOGIC
POWER-DOWN
LOGIC
BUF
GAIN
DB
7
DB
0
.
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD
GND
AD5330
POWER-ON
RESET
RESET
FEATURES
AD5330: Single 8-Bit DAC in 20-Lead TSSOP
AD5331: Single 10-Bit DAC in 20-Lead TSSOP
AD5340: Single 12-Bit DAC in 24-Lead TSSOP
AD5341: Single 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 115 A @ 3 V, 140 A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via
PD
Pin
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–V
REF
or 0–2 V
REF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via
LDAC
Pin
Asynchronous
CLR
Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 115
μ
A at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both
supply rails, while the AD5330, AD5340, and AD5341 allow a
choice of buffered or unbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel interface.
CS
selects the device and data is loaded into the input registers
on the rising edge of
WR
.
The GAIN pin allows the output range to be set at 0 V to V
REF
or 0 V to 2
×
V
REF
.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the
LDAC
pin.
An asynchronous
CLR
input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in Thin
Shrink Small Outline Packages (TSSOP).
*
Protected by U.S. Patent Number 5,969,657; other patents pending.
相關(guān)PDF資料
PDF描述
AD5341 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
AD5341BRU 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
AD5342 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
AD5342BRU 2.5 V to 5.5 V, 230uA, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs
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