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參數(shù)資料
| 型號： | AD5335BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.5 V to 5.5 V, 500 uA, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs |
| 中文描述： | QUAD, PARALLEL, 8 BITS INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 359K |
| 代理商： | AD5335BRU |
REV. 0
AD5330/AD5331/AD5340/AD5341
–15–
The low data byte of the AD5341 consists of data bits 0 to 7 at
data inputs DB
0
to DB
7
, while the high byte consists of data
bits 8 to 11 at data inputs DB
0
to DB
3
as shown in Figure 29.
DB
4
to DB
7
are ignored during a high-byte write, but they may
be used for data to set up the reference input as buffered/
unbuffered, and buffer amplifier gain. See Figure 33.
DB8
DB9
X
X
HIGH BYTE
LOW BYTE
X = UNUSED BIT
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
X
X
DB10
DB11
Figure 29. Data Format for AD5341
POWER-ON RESET
The AD5330/AD5331/AD5340/AD5341 are provided with a
power-on reset function, so that they power up in a defined state.
The power-on state is:
Normal Operation
Reference Input Unbuffered
0 – V
REF
Output Range
Output Voltage Set to 0 V
Both input and DAC registers are filled with zeros and remain so
until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
POWER-DOWN MODE
The AD5330/AD5331/AD5340/AD5341 have low power con-
sumption, dissipating only 0.35 mW with a 3 V supply and
0.7 mW with a 5 V supply. Power consumption can be further
reduced when the DAC is not in use by putting it into power-
down mode, which is selected by taking pin
PD
low.
When the
PD
pin is high, the DAC works normally with a
typical power consumption of 140
μ
A at 5 V (115
μ
A at 3 V).
In power-down mode, however, the supply current falls to
200 nA at 5 V (80 nA at 3 V) when the DAC is powered-down.
Not only does the supply current drop, but the output stage is
also internally switched from the output of the amplifier mak-
ing it open-circuit. This has the advantage that the output is
three-state while the part is in power-down mode and pro-
vides a defined input condition for whatever is connected to
the output of the DAC amplifier. The output stage is illus-
trated in Figure 30.
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
V
OUT
Figure 30. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string,
and all other associated linear circuitry are shut down when
the power-down mode is activated. However, the contents
of the registers are unaffected when in power-down. The time
to exit power-down is typically 2.5
μ
s for V
DD
= 5 V and 5
μ
s
when V
DD
= 3 V. This is the time from a rising edge on the
PD
pin to when the output voltage deviates from its power-
down voltage. See Figure 22.
Table I. AD5330/AD5331/AD5340 Truth Table
CLR
LDAC
CS
WR
Function
1
1
0
1
1
1
1
1
X
1
0
0
1
X
X
0
0
X
X
1
X
0
1
0
1
X
No Data Transfer
No Data Transfer
Clear All Registers
Load Input Register
Load Input Register and DAC Register
Update DAC Register
X = don’t care.
Table II. AD5341 Truth Table
CLR
LDAC
CS
WR
HBEN
Function
1
1
0
1
1
1
1
1
1
1
X
1
1
0
0
0
1
X
X
0
0
0
0
X
X
1
X
0
1
0
1
0
1
0
1
X
X
X
X
0
1
0
1
X
No Data Transfer
No Data Transfer
Clear All Registers
Load Low-Byte Input Register
Load High-Byte Input Register
Load Low-Byte Input Register and DAC Register
Load High-Byte Input Register and DAC Register
Update DAC Register
X = don’t care.
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