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參數(shù)資料
| 型號： | AD5331 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
| 中文描述： | 2.5 V至5.5 V，115微安，并行接口單電壓輸出DAC的8-/10-/12-Bit |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 359K |
| 代理商： | AD5331 |
REV. 0
AD5330/AD5331/AD5340/AD5341
–9–
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL versus Code plot can be seen in Figures
5, 6, and 7.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of
±
1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Typical DNL versus Code plot can be seen in
Figures 8, 9, and 10.
GAIN ERROR
This is a measure of the span error of the DAC (including any
error in the gain of the buffer amplifier). It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
expressed as a percentage of the full-scale range. This is illus-
trated in Figure 2.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
If the offset voltage is positive, the output voltage will still be
positive at zero input code. This is shown in Figure 3. Because
the DACs operate from a single supply, a negative offset cannot
appear at the output of the buffer amplifier. Instead, there will
be a code close to zero at which the amplifier output saturates
(amplifier footroom). Below this code there will be a deadband
over which the output voltage will not change. This is illustrated
in Figure 4.
OUTPUT
VOLTAGE
DAC CODE
POSITIVE
GAIN ERROR
ACTUAL
IDEAL
NEGATIVE
GAIN
ERROR
Figure 2. Gain Error
OUTPUT
VOLTAGE
DAC CODE
POSITIVE
OFFSET
GAIN ERROR
AND
OFFSET ERROR
ACTUAL
IDEAL
Figure 3. Positive Offset Error and Gain Error
OUTPUT
VOLTAGE
DAC CODE
NEGATIVE
OFFSET
GAIN ERROR
AND
OFFSET ERROR
ACTUAL
IDEAL
AMPLIFIER
FOOTROOM
(~1mV)
NEGATIVE
OFFSET
DEADBAND CODES
Figure 4. Negative Offset Error and Gain Error
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD5331BRU | 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
| AD5335 | 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
| AD5335BRU | 2.5 V to 5.5 V, 500 uA, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs |
| AD5336 | 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
| AD5336BRU | 2.5 V to 5.5 V, 500 uA, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5331BRU | 制造商:Analog Devices 功能描述:DAC 1-CH Resistor-String 10-bit 20-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:10-BIT,SINGLE DAC I.C - Bulk 制造商:Analog Devices 功能描述:IC 10BIT DAC SMD 5331 TSSOP20 |
| AD5331BRU-REEL | 制造商:Analog Devices 功能描述:DAC 1-CH Resistor-String 10-bit 20-Pin TSSOP T/R |
| AD5331BRU-REEL7 | 制造商:Analog Devices 功能描述:DAC 1-CH Resistor-String 10-bit 20-Pin TSSOP T/R |
| AD5331BRUZ | 功能描述:IC DAC 10BIT SNGL VOUT 20TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD5331BRUZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 115 ??A, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
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