參數(shù)資料
型號: AD5323ARUZ
廠商: Analog Devices Inc
文件頁數(shù): 23/28頁
文件大?。?/td> 0K
描述: IC DAC 12BIT DUAL R-R 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準包裝: 96
設(shè)置時間: 8µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 2.5mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): 125k
AD5303/AD5313/AD5323
Rev. B | Page 4 of 28
A Version1
B Version1
Parameter2
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
LOGIC INPUTS5
Input Current
±1
μA
0.8
V
VDD = 5 V ± 10%
0.6
V
VDD = 3 V ± 10%
Input Low Voltage, VIL
0.5
V
VDD = 2.5 V
2.4
V
VDD = 5 V ± 10%
2.1
V
VDD = 3 V ± 10%
Input High Voltage, VIH
2.0
V
VDD = 2.5 V
Pin Capacitance
2
3.5
2
3.5
pF
LOGIC OUTPUT (SDO)5
VDD = 5 V ± 10%
Output Low Voltage
0.4
V
ISINK = 2 mA
Output High Voltage
4.0
V
ISOURCE = 2 mA
VDD = 3 V ± 10%
Output Low Voltage
0.4
V
ISINK = 2 mA
Output High Voltage
2.4
V
ISOURCE = 2 mA
Floating-State Leakage Current
1
μA
DCEN = GND
Floating-State Output
Capacitance
3
pF
DCEN = GND
POWER REQUIREMENTS
VDD
2.5
5.5
2.5
5.5
V
IDD specification is valid for all DAC codes
IDD (Normal Mode)
Both DACs active and excluding load
currents
VDD = 4.5 V to 5.5 V
300
450
300
450
μA
VDD = 2.5 V to 3.6 V
230
350
230
350
μA
Both DACs in unbuffered mode;
VIH = VDD and VIL = GND; in buffered
mode, extra current is typically x μA
per DAC, where x = 5 μA + VREF/RDAC
IDD (Full Power-Down)
VDD = 4.5 V to 5.5 V
0.2
1
0.2
1
μA
VDD = 2.5 V to 3.6 V
0.05
1
0.05
1
μA
1 Temperature range for Version A, Version B: 40°C to +105°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5303 (Code 8 to Code 248); AD5313 (Code 28 to Code 995); AD5323 (Code 115 to Code 3981).
5 Guaranteed by design and characterization, not production tested.
6 In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD
and offset plus gain error must be positive.
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