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參數(shù)資料
| 型號： | AD5313BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DUAL R-R 16-TSSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 2,500 |
| 設置時間： | 7µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 143k |
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AD5303/AD5313/AD5323
Rev. B | Page 23 of 28
COARSE AND FINE ADJUSTMENT USING THE
AD5303/AD5313/AD5323
The DACs in the AD5303/AD5313/AD5323 can be paired
together to form a coarse and fine adjustment function, as
shown in Figure 45. DAC A provides the coarse adjustment
while DAC B provides the fine adjustment. Varying the ratio
of R1 and R2 changes the relative effect of the coarse and fine
adjustments. With the resistor values and external reference
shown, the output amplifier has unity gain for the DAC A
output, so the output range is 0 V to 2.5 V 1 LSB. For
DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B
a range equal to 19 mV.
The circuit is shown with a 2.5 V reference, but reference
voltages up to VDD may be used. The op amps indicated allow
a rail-to-rail output swing.
GND
AD5303/AD5313/
AD5323
EXT 2.5V
REF
00
47
2-
0
45
VOUT
VOUTB
VREFA
1F
GND
VIN
0.1F
10F
VDD
VDD = 5V
+5V
AD820/
OP295
VOUTA
VREFB
R2
51.2k
R1
390
VOUT
R4
900
R3
51.2k
AD780/REF192
WITH VDD = 5V
Figure 45. Coarse and Fine Adjustment
DAISY-CHAIN MODE
This mode is used for updating serially connected or standalone
devices on the rising edge of SYNC. For systems that contain
several DACs, or where the user wishes to read back the DAC
contents for diagnostic purposes, the SDO pin may be used to
daisy-chain several devices together and provide serial readback.
By connecting the daisy-chain enable (DCEN) pin high, the
daisy-chain mode is enabled. It is tied low in standalone mode.
In daisy-chain mode, the internal gating on SCLK is disabled.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than 16 clock pulses are applied,
the data ripples out of the shift register and appears on the SDO
line. This data is clocked out after the falling edge of SCLK and
is valid on the subsequent rising and falling edges. By connect-
ing this line to the DIN input on the next DAC in the chain, a
multiDAC interface is constructed. Sixteen clock pulses are
required for each DAC in the system. Therefore, the total
number of clock cycles must equal 16N, where N is the total
number of devices in the chain. When the serial transfer to all
devices is complete, SYNC should be taken high. This prevents
any further data from being clocked into the input shift register.
A continuous SCLK source may be used if it can be arranged
that SYNC is held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of
clock cycles may be used and SYNC may be taken high some
time later.
When the transfer to all input registers is complete, a common
LDAC signal updates all DAC registers and all analog outputs
are updated simultaneously.
00
47
2-
0
46
68HC111
MISO
MOSI
SCK
PC7
PC6
DIN
SCLK
AD5303/
AD5313/
AD53231
(DAC 1)
SYNC
LDAC
SDO
SCLK
AD5303/
AD5313/
AD53231
(DAC 2)
SYNC
LDAC
SDO
DIN
SCLK
AD5303/
AD5313/
AD53231
(DAC N)
SYNC
LDAC
SDO
DIN
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. Daisy-Chain Mode
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| AD5313RBRUZ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 10-Bit 2-ch SPI nanoDAC+with on-chip ref RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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