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參數(shù)資料
| 型號： | AD5302ARM-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL R-R 10-MSOP TR |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 167k |
AD5302/AD5312/AD5322
Rev. D | Page 4 of 24
A Version1
B Version1
Parameter2
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.5
5.5
2.5
5.5
V
IDD specification is valid for all DAC codes
IDD (Normal Mode)
Both DACs active and excluding load currents
VDD = 4.5 V to 5.5 V
300
450
300
450
μA
Both DACs in unbuffered mode, VIH = VDD and
VDD = 2.5 V to 3.6 V
230
350
230
350
μA
VIL = GND; in buffered mode, extra current is
typically × μA per DAC where x = 5 μA + VREF/RDAC
IDD (Full Power-Down)
VDD = 4.5 V to 5.5 V
0.2
1
0.2
1
μA
VDD = 2.5 V to 3.6 V
0.05
1
0.05
1
μA
1 Temperature range: A, B version: –40°C to +105°C.
2 See Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981).
5 Guaranteed by design and characterization, not production tested.
6 In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage,
VREF = VDD and offset plus gain error must be positive.
AC SPECIFICATIONS
VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1
Table 2.
Min
Typ
Max
Unit
Test Conditions/Comments
Output Voltage Settling Time
VREF = VDD = 5 V
AD5302
6
8
μs
Scale to Scale Change (0 × 40 to 0 × C0)
AD5312
7
9
μs
Scale to Scale Change (0 × 100 to 0 × C300)
AD5322
8
10
μs
Scale to Scale Change (0 × 400 to 0 × C00)
Slew Rate
0.7
V/μs
Major-Code Transition Glitch Energy
12
nV-s
1 LSB Change Around Major Carry (011…11 to 100…00)
Digital Feedthrough
0.10
nV-s
Analog Crosstalk
0.01
nV-s
DAC-to-DAC Crosstalk
0.01
nV-s
Multiplying Bandwidth
200
kHz
VREF = 2 V ± 0.1 V p-p, Unbuffered Mode
Total Harmonic Distortion
70
dB
VREF = 2.5 V ± 0.1 V p-p, Frequency = 10 kHz
1 Guaranteed by design and characterization, not production tested.
2 Temperature range: A, B version: 40°C to +105°C.
3 See Terminology section.
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