參數(shù)資料
型號(hào)： AD5301BRM-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 1/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC 8BIT 2WIRE I2C 8-MSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 1,000
設(shè)置時(shí)間： 6µs
位數(shù)： 8
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 1.4mW
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 1 電壓，單極；1 電壓，雙極
采樣率（每秒）： 167k
2.5 V to 5.5 V, 120 μA, 2-Wire Interface,
Voltage-Output 8-/10-/12-Bit DACs
AD5301/AD5311/AD5321
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
1999–2007 Analog Devices, Inc. All rights reserved.
FEATURES
AD5301: buffered voltage output 8-bit DAC
AD5311: buffered voltage output 10-bit DAC
AD5321: buffered voltage output 12-bit DAC
6-lead SOT-23 and 8-lead MSOP packages
Micropower operation: 120 μA @ 3 V
2-wire (I2C-compatible) serial interface
Data readback capability
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 50 nA @ 3 V
Reference derived from power supply
Power-on reset to 0 V
On-chip rail-to-rail output buffer amplifier
3 power-down functions
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5301/AD5311/AD53211 are single 8-/10-/12-bit, buff-
ered, voltage-output DACs that operate from a single 2.5 V to
5.5 V supply, consuming 120 μA at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of
0.7 V/μs. It uses a 2-wire (I2C-compatible) serial interface that
operates at clock rates up to 400 kHz. Multiple devices can share
the same bus.
The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
parts incorporate a power-on reset circuit, which ensures that
the DAC output powers up to 0 V and remains there until a
valid write takes place. The parts contain a power-down feature
that reduces the current consumption of the device to 50 nA at
3 V and provides software-selectable output loads while in
power-down mode.
The low power consumption in normal operation makes these
DACs ideally suited to portable battery-operated equipment. The
power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V,
reducing to 1 μW in all power-down modes.
1 Protected by U.S. Patent No. 5684481.
FUNCTIONAL BLOCK DIAGRAM
RESISTOR
NETWORK
BUFFER
DAC
REGISTER
POWER-DOWN
LOGIC
AD5301/AD5311/AD5321
VDD
SCL
A0
GND
A1*
REF
POWER-ON
RESET
PD*
SDA
*AVAILABLE ON 8-LEAD VERSION ONLY
INTERFACE
LOGIC
8-/10-/12-BIT
DAC
VOUT
00
92
7-
0
01
Figure 1.
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