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參數(shù)資料
| 型號： | AD5301 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
| 中文描述： | 2.5 V至5.5 V，115微安，并行接口單電壓輸出DAC的8-/10-/12-Bit |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 359K |
| 代理商： | AD5301 |
REV. 0
–3–
AD5330/AD5331/AD5340/AD5341
AC CHARACTERISTICS
1
B Version
3
Min
Parameter
2
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
AD5330
AD5331
AD5340
AD5341
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Multiplying Bandwidth
Total Harmonic Distortion
V
REF
= 2 V. See Figure 20
1/4 Scale to 3/4 Scale Change (40 H to C0 H)
1/4 Scale to 3/4 Scale Change (100 H to 300 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
6
7
8
8
0.7
6
0.5
200
–70
8
9
10
10
μ
s
μ
s
μ
s
μ
s
V/
μ
s
nV-s
nV-s
kHz
dB
1 LSB Change Around Major Carry
V
REF
= 2 V
±
0.1 V p-p. Unbuffered Mode
V
REF
= 2.5 V
±
0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology section.
3
Temperature range: B Version: –40
°
C to +105
°
C; typical specifications are at 25
°
C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
Parameter
Limit at T
MIN
, T
MAX
0
0
20
5
4.5
5
5
4.5
5
4.5
20
20
50
Unit
Condition/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CS
to
WR
Setup Time
CS
to
WR
Hold Time
WR
Pulsewidth
Data, GAIN, BUF, HBEN Setup Time
Data, GAIN, BUF, HBEN Hold Time
Synchronous Mode.
WR
Falling to
LDAC
Falling.
Synchronous Mode.
LDAC
Falling to
WR
Rising.
Synchronous Mode.
WR
Rising to
LDAC
Rising.
Asynchronous Mode.
LDAC
Rising to
WR
Rising.
Asynchronous Mode.
WR
Rising to
LDAC
Falling.
LDAC
Pulsewidth
CLR
Pulsewidth
Time Between
WR
Cycles
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 1.
CS
WR
DATA,
GAIN,
BUF,
HBEN
LDAC
1
LDAC
2
CLR
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
NOTES:
1
SYNCHRONOUS
LDAC
UPDATE MODE
2
ASYNCHRONOUS
LDAC
UPDATE MODE
Figure 1. Parallel Interface Timing Diagram
(V
DD
= 2.5 V to 5.5 V, All specifications T
MIN
to T
MAX
unless otherwise noted.)
(V
DD
= 2.5 V to 5.5 V. R
L
= 2 k to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
unless otherwise noted.)
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