參數(shù)資料
型號(hào)： AD5292BRUZ-100-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/32頁(yè)
文件大小： 0K
描述： IC DGTL POT 1024POS 20K 14TSSOP
設(shè)計(jì)資源： Variable Gain Noninverting Amplifier Using AD5292 and OP184 (CN0112)
Variable Gain Inverting Amplifier Using AD5292 and OP184 (CN0113)
Low Cost, High Voltage, Programmable Gain Instrumentation Amplifier Using AD5292 and AD8221 (CN0114)
Programmable High Voltage Source with Boosted Output Current Using AD5292, OP184, and MOSFETs (CN0115)
Programmable Bidirectional Current Source Using AD5292 and ADA4091-4 (CN0117)
Logarithmic Audio Volume Control with Glitch Reduction Using AD5292 (CN0120)
標(biāo)準(zhǔn)包裝： 1,000
接片： 1024
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型： 非易失
接口： 4 線串行
電源電壓： 9 V ~ 33 V，±9 V ~ 16.5 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
AD5291/AD5292
Rev. D | Page 26 of 32
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—1% Resistor Tolerance
The AD5291 and AD5292 operate in rheostat mode when only
two terminals are used as a variable resistor. The unused
terminal can be left floating or tied to the W terminal, as shown in
W
A
B
W
A
B
W
A
B
0
7
67
4-
05
2
Figure 66. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 20 kΩ, 50 kΩ, and 100 kΩ, and 256 or 1024
tap points accessed by the wiper terminal. The 8-/10-bit data in
the RDAC latch is decoded to select one of the 256/1024
possible wiper settings. The AD5291 and AD5292 contain an
internal ±1% resistor performance mode that can be disabled or
enabled (this is enabled by default), by programming Bit C2 of
the control register (see Table 13 and Table 14). The digitally
programmed output resistance between the W terminal and the
A terminal, RWA, and between the W terminal and B terminal,
RWB, is internally calibrated to give a maximum of ±1% absolute
resistance error across a wide code range. As a result, the
general equations for determining the digitally programmed
output resistance between the W terminal and B terminal are
AD5291:
AB
WB
R
D
R
×
=
256
)
(
(1)
AD5292:
AB
WB
R
D
R
×
=
1024
)
(
(2)
where:
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
RAB is the end-to-end resistance.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the W terminal and the A terminal also produces a
digitally controlled complementary resistance, RWA. RWA is also
calibrated to give a maximum of 1% absolute resistance error.
RWA starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equations for
this operation are
AD5291:
AB
WA
R
D
R
×
=
256
)
(
(3)
AD5292:
AB
WA
R
D
R
×
=
1024
)
(
(4)
where:
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
RAB is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of 120 Ω
is present. Regardless of which setting the part is operating in,
take care to limit the current between Terminal A and Terminal B,
between Terminal W and Terminal A, and between Terminal W
and Terminal B, to the maximum continuous current of ±3 mA or
to the pulse current specified in Table 8. Otherwise, degradation
or possible destruction of the internal resistors may occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
the wiper to B and at the wiper to A that is proportional to the
input voltage at A to B, as shown in Figure 67. Unlike the polarity
of VDD to GND, which must be positive, voltage across A to B,
W to A, and W to B can be at either polarity.
W
A
B
VIN
VOUT
07
67
4-
05
3
Figure 67. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity, con-
necting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is
equal to the voltage applied across Terminal A and Terminal B,
divided by the 256/1024 positions of the potentiometer divider.
The general equations defining the output voltage at VW with
respect to ground for any valid input voltage applied to Terminal A
and Terminal B are
AD5291:
B
A
W
V
D
V
D
V
×
+
×
=
256
)
(
(5)
AD5292:
B
A
W
V
D
V
D
V
×
+
×
=
1024
)
(
(6)
If using the AD5291 and AD5292 in voltage divider mode as
shown in Figure 67, then the ±1% resistor tolerance calibration
feature reduces the error when matching with discrete resistors.
However, it is recommended to disable the internal ±1% resistor
tolerance calibration feature by programming Bit C2 of the
control register (see Table 13 and Table 14) to optimize wiper
position update rate. In this configuration, the RDAC is ratiome-
tric and resistor tolerance error does not affect performance.
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