參數(shù)資料
型號: AD5290YRMZ10-R7
廠商: Analog Devices Inc
文件頁數(shù): 17/20頁
文件大?。?/td> 0K
描述: IC POT DGTL 10KW 256POS 10-MSOP
標準包裝: 1,000
接片: 256
電阻(歐姆): 10k
電路數(shù): 1
溫度系數(shù): 標準值 35 ppm/°C
存儲器類型: 易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 4.5 V ~ 30 V,±4.5 V ~ 15 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 10-MSOP
包裝: 帶卷 (TR)
配用: EVAL-AD5290EBZ-ND - BOARD EVAL FOR AD5290
AD5290
Data Sheet
Rev. C | Page 6 of 20
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS6, 8, 9
Bandwidth 3 dB
BW
RAB = 50 k, code = 0x80
90
kHz
RAB = 100 k, code = 0x80
50
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
0.002
%
VW Settling Time
tS
VA = 10 V, VB = 0 V,
±1 LSB error band
4
s
Resistor Noise Voltage
eN_WB
RWB = 25 k, f = 1 kHz
20
nV√Hz
1
Typical represents average reading at +25°C, VDD = +15 V, and VSS = 15 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.
3
All parts have a 35 ppm/°C temperature coefficient.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification
limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
PDISS is calculated from (IDD × VDD) + abs (ISS × VSS). CMOS logic level inputs result in minimum power dissipation.
8
Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use VDD = +15 V and VSS = 15 V.
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