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參數(shù)資料
| 型號(hào)： | AD5290EVAL |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 數(shù)字電位計(jì) |
| 英文描述： | Compact +30V/【15V 256-Position Digital Potentiometer |
| 中文描述： | 緊湊型30V的/【15V的256位數(shù)字電位器 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | AD5290EVAL |
Preliminary Technical Data
AD5290
Rev. Pr C | Page 9 of 11
A
V
I
W
B
V
O
0
Figure 7. Potentiometer Mode Configuration
Ignoring the effect of the wiper resistance, the
transfer function
is simply
A
W
V
256
D
)
D
(
V
=
(3)
A more accurate calculation, which includes the wiper
resistance effect, yields
A
W
W
AB
W
V
R
2
R
R
256
R
D
)
D
(
V
+
+
=
AB
(4)
If there is an applied voltage at the B terminal, then the transfer
function becomes
B
A
W
V
D
V
D
256
D
V
256
256
)
(
+
=
(5)
Unlike in rheostat mode operation where the absolute tolerance
is high, potentiometer mode operation yields an almost ratio-
metric function of D/256 with a relatively small error contributed
by the RW terms, and therefore the tolerance effect is almost
cancelled. Although the thin film step resistor R
S
and CMOS
switches resistance R
W
have very different temperature coeffi-
cients, the ratiometric adjustment also reduces the overall
temperature coefficient effect to 5 ppm/°C, except at low value
codes where R
W
dominates.
Potentiometer mode operations include others such as op amp
input, feedback resistor networks, and other voltage scaling
applications. A, W, and B terminals can in fact be input or
output terminals provided that |V
A
|, |V
W
|, and |V
B
| do not
exceed |V
DD
| and |V
SS
|.
SPI COMPATIBLE 3-WIRE SERIAL BUS
The AD5290 contains a 3-wire SPI compatible digital interface
(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in Table .
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. CS should start high, when it
goes low, the clock loads data into the serial register on each
positive clock edge (see Figure 3).
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5290 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS returns to logic high. If
dataword contains more than 8-bit, the extra MSB bits will be
ignored.
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in 8 and Figure 9. This
applies to the digital input pins SDI, CLK, and CS.
LOGIC
340
V
SS
Figure 8. ESD Protection of Digital Pins
A,B,W
V
SS
Figure 9. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5290 V
DD
and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed V
DD
or GND will be clamped by the internal forward
biased diodes (see Figure 10).
A
V
DD
B
W
V
SS
Figure 10. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 10), it is important to power
V
DD
–to-GND and V
SS
-to-GND before applying any voltage to
terminals A, B, and W; otherwise, the diode will be forward
biased such that V
DD
will be powered unintentionally and may
affect the rest of the user’s circuit. The ideal power-up sequence
is in the following order: GND, V
SS
,V
DD
, digital inputs, and then
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| AD5290YRMZ100 | 功能描述:IC DGTL POT 100K 256POS 10MSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲(chǔ)器類(lèi)型:非易失 接口:3 線(xiàn)串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:1399 (CN2011-ZH PDF) 其它名稱(chēng):MAX5423ETA+TCT |
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