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| 型號： | AD5282BRU200 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 10-Bit, 40MSPS ADC Dual Ch., Low Power 48-TQFP -40 to 85 |
| 中文描述： | DUAL 200K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 156K |
| 代理商： | AD5282BRU200 |
PRELIMINARY TECHNICAL DATA
AD5280/AD5282
REV PrE 12 MAR 02
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com
3
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION
(V
DD
=
+5
V, V
SS
= -
5
V, V
LOGIC
=
+5
V,
V
A
= +V
DD
, V
B
= 0V, -40°C < T
A
< +85°C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
DYNAMIC CHARACTERISTICS
6,9,11
Bandwidth –3dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage
BW_20K
BW_50K
BW_200K
THD
W
t
S
e
N_WB
R
AB
= 20K
,
Code = 80
H
R
AB
= 50K
,
Code = 80
H
R
AB
= 200K
,
Code = 80
H
V
A
=1Vrms + 2V dc, V
B
= 2V DC, f=1KHz
V
A
= V
DD
, V
B
=0V, ±1 LSB error band
R
WB
= 10K
, f = 1KHz
650
142
69
0.005
2
14
kHz
kHz
kHz
%
μs
nV
√
Hz
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
SCL Clock Frequency
t
BUF
Bus free time between
STOP & START
t
HD;STA
Hold Time (repeated START)
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time For START Condition t5
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of both SDA & SCL signals
t
R
Rise Time of both SDA & SCL signals
t
SU;STO
Setup time for STOP Condition
f
SCL
t1
t2
t3
t4
After this period the first clock pulse is generated
0
1.3
0.6
1.3
0.6
0.6
0
100
0.6
400
0.9
300
300
KHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
t6
t7
t8
t9
t10
NOTES:
1.
2.
Typicals represent average readings at +25°C, V
DD
= +5V, V
SS
= -5V.
Resistor position nonlinearity error R-INL is the deviation froman ideal value measured between the maximumresistance and the mnimumresistance wiper positions. R-DNL measures the
relative step change fromideal between successive tap positions. Parts are guaranteed monotonic.
V
AB
= V
DD
, Wiper (V
W
) = No connect
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider simlar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0V.
DNL specification limts of ±1LSB maximumare Guaranteed Monotonic operating conditions.
Resistor termnals A,B,W have no limtations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Bandwidth, noise and settling time are dependent on the termnal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value
result in the mnimumoverall power consumption.
PDISS is calculated from(IDD x VDD). CMOS logic level inputs result in mnimumpower dissipation.
All dynamc characteristics use V
DD
= +5V.
See timng diagramfor location of measured values.
3.
4.
5.
6.
9.
10.
11.
12.
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