參數(shù)資料
型號(hào)： AD5273EVAL
廠商： Analog Devices, Inc.
元件分類(lèi)： 數(shù)字電位計(jì)
英文描述： 64-Position OTP Digital Potentiometer
中文描述： 64工位檢察官數(shù)字電位器
文件頁(yè)數(shù)： 3/20頁(yè)
文件大小： 987K
代理商： AD5273EVAL
AD5273
–3–
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DYNAMIC CHARACTERISTICS
6, 10, 11
Bandwidth –3 dB
BW_1 k
BW_10 k
BW_50 k
BW_100 k
R
AB
= 100 k
, Code = 20
H
THD
W
V = 1 V rms, R
AB
= 1 k
,
V
B
= 0 V, f = 1 kHz
t
S1
V = 5 V ± 1 LSB Error Band, V
B
= 0,
Measured at V
W
t
S_OTP
V = 5 V ± 1 LSB Error Band, V
B
= 0,
Measured at V
W
R
AB
= 1 k
, Code = 20
H
R
AB
= 10 k
, Code = 20
H
R
AB
= 50 k
, Code = 20
H
6000
600
110
60
kHz
kHz
kHz
kHz
Total Harmonic Distortion
0.014
%
Adjustment Settling Time
5
μs
OTP Settling Time
12
400
ms
Power-Up Settling Time –
Post Fuses Blown
t
S2
V = 5 V ± 1 LSB Error Band, V
B
= 0,
Measured at V
W
R = 1 k
, f = 1 kHz, Code = 20
H
R = 20 k , f = 1 kHz, Code = 20
H
R = 50 k , f = 1 kHz, Code = 20
H
R = 100 k , f = 1 kHz, Code = 20
H
5
3
13
20
28
μs
nV/
Hz
√
nV/
Hz
√
nV/
Hz
√
nV/
Hz
√
Resistor Noise Voltage
e
N_WB
INTERFACE TIMING CHARACTERISTICS (applies to all parts
6, 11, 13
)
SCL Clock Frequency
t
BUF
Bus Free Time between
STOP and START
t
HD;STA
Hold Time
(repeated START)
SCL
f
400
kHz
t
1
1.3
μs
t
2
After this period, the first clock
pulse is generated.
0.6
1.3
0.6
μs
μs
μs
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for START
Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and
SCL Signals
t
Rise Time of Both SDA and
R
SCL Signals
t
SU;STO
Setup Time for STOP
Condition
t
3
t
4
50
t
5
t
6
t
7
0.6
μs
μs
μs
0.9
0.1
t
8
0.3
μs
t
9
0.3
μs
t
10
0.6
μs
NOTES
Typicals represent average readings at 25°C, V
= 5 V, V
= 0 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V = V
, Wiper (V
) = No Connect.
4
INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V = V
limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Different from operating power supply, power supply for OTP is used one time only.
8
Different from operating current, supply current for OTP lasts approximately 400 ms for one time needed only.
9
P
is calculated from (I
V
). CMOS logic level inputs result in minimum power dissipation.
10
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
11
All dynamic characteristics use V
= 5 V.
12
Different from settling time after fuses are blown. The OTP settling time occurs once only.
13
See Figure 1 for location of measured values.
DD
and V
B
= 0 V. DNL specification
Specifications subject to change without notice.
REV. 0
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