參數(shù)資料
型號(hào)： AD526SD
廠商： ANALOG DEVICES INC
元件分類： 運(yùn)動(dòng)控制電子
英文描述： 8 channel, 10 Bit, 40MSPS ADC, 1.8V 257-BGA MICROSTAR 0 to 70
中文描述： INSTRUMENTATION AMPLIFIER, 800 uV OFFSET-MAX, 4 MHz BAND WIDTH, CDIP16
封裝： HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-16
文件頁(yè)數(shù)： 9/14頁(yè)
文件大?。?/td> 464K
代理商： AD526SD
AD526
REV. D
–9–
The specifications on page 3, in combination with Figure 35,
give the timing requirements for loading new gain codes.
VALID DATA
GAIN CODE
INPUTS
CLK
OR
CS
T
C
T
H
T
S
T
C
= MINIMUM CLOCK CYCLE
T
S
= DATA SETUP TIME
T
H
= DATA HOLD TIME
NOTE: THRESHOLD LEVEL FOR
GAIN CODE,
CS
, AND
CLK
IS 1.4V.
Figure 35. AD526 Timing
TIMING AND CONTROL
Table I. Logic Input Truth Table
Gain Code
A2 A1 A0 B
Control
CLK
(
CS
= 0)
Condition
Gain
Condition
X
0
0
0
0
1
X
X
0
0
0
0
1
X
0
0
1
1
X
X
X
0
0
1
1
X
X
0
1
0
1
X
X
X
0
1
0
1
X
X
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
Previous State
1
2
4
8
16
1
1
1
2
4
8
16
Latched
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Latched
Latched
Latched
Latched
Latched
Latched
NOTE: X = Don’t Care.
DIGITAL FEEDTHROUGH
With either
CS
or
CLK
or both held high, the AD526 gain state
will remain constant regardless of the transitions at the A0, A1,
A2 or B inputs. However, high speed logic transitions will un-
avoidably feed through to the analog circuitry within the AD526
causing spikes to occur at the signal output.
This feedthrough effect can be completely eliminated by operat-
ing the AD526 in the transparent mode and latching the gain
code in an external bank of latches (Figure 36).
To operate the AD526 using serial inputs, the configuration
shown in Figure 36 can be used with the 74LS174 replaced by a
serial-in/parallel-out latch, such as the 54LS594.
OUT
FORCE
OUT
SENSE
V
OUT
0.1
m
F
–V
S
0.1
m
F
+V
S
+5V
V
IN
74LS174
1
m
F
B
A2
A0
A1
TIMING
SIGNAL
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
+
–
AD526
16
8
4
2
1
GAIN NETWORK
A1
A0
LOGIC AND LATCHES
CS
CLK
A2
B
Figure 36. Using an External Latch to Minimize Digital
Feedthrough
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