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參數(shù)資料
| 型號： | AD526J |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Software Programmable Gain Amplifier |
| 中文描述： | 軟件可編程增益放大器 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 464K |
| 代理商： | AD526J |
AD526
REV. D
–13–
HIGH ACCURACY A/D CONVERTERS
Very high accuracy and high resolution floating-point A/D con-
verters can be achieved by the incorporation of offset and gain
calibration routines. There are two techniques commonly used
for calibration, a hardware circuit as shown in Figure 43 and/or
a software routine. In this application the microprocessor is
functioning as the autoranging circuit, requiring software over-
head; therefore, a hardware calibration technique was applied
which reduces the software burden. The software is used to set
the gain of the AD526. In operation the signal is converted, and
if the MSB of the AD574 is not equal to a Logical 1, the gain is
increased by binary steps, up to the maximum gain. This maxi-
mizes the full-scale range of the conversion process and insures
a wide dynamic range.
The calibration technique uses two point correction, offset and
gain. The hardware is simplified by the use of programmable
magnitude comparators, the 74ALS528s, which can be “burned”
for a particular code. In order to prevent under or over range
hunting during the calibration process, the reference offset and
gain codes should be different from the endpoint codes. A cali-
bration cycle consists of selecting whether gain or offset is to be
calibrated then selecting the appropriate multiplexer channel to
apply the reference voltage to the signal channel. Once the op-
eration has been initiated, the counter, a 74ALS869, drives the
D/A converter in a linear fashion providing a small correction
voltage to either the gain or offset trim point of the AD574. The
output of the A/D converter is then compared to the value pre-
set in the 74ALS528 to determine a match. Once a match is
detected, the 74ALS528 produces a low going pulse which stops
the counter. The code at the D/A converter is latched until the
next calibration cycle. Calibration cycles are under the control
of the microprocessor in this application and should be imple-
mented only during periods of converter inactivity.
A2
A1
A4
A3
AD588
R4
NOISE
REDUCTION
R8
R1
R2
R3
R5
R6
1
m
F
+V
S
–V
S
–5V
+5V
+15V
–15V
SYS
GND
0.1
m
F
0.1
m
F
AD7501
V
IN1
V
IN2
V
IN3
V
IN4
DECODED
ADDRESS
AD526
DECODED
ADDRESS
WR
WR
ADDRESS BUS
10k
V
–15V +15V
AD585
–15V +15V
200pF
F
S
2
1
7404
OP27
+15V
–15V
V
REF
DE-
CODED
ADD
WR
+
+
+15V
–15V
+5V
10
m
F
10
m
F
MSB
LSB
+5V
50k
V
1k
V
AD574
DATA
BUS
12
12
MSB
LSB
74ALS
528
GAIN
P = Q
+5V
MSB
LSB
74ALS
528
OFFSET
P = Q
+5V
7475
7475
1/2
+5V
+5V
7475
1/2
7400
1
2
3
7400
6
4
5
PIN 28
AD574
ADG221
CLOGIC
INPUT
BUFFER
LATCH
DAC A
LATCH
DAC B
AD7628
WR
A
/B
V
REF
V
REF
WR
7869
MSB
LSB
CALIBRATION
VALUE
+5V
+5V
5k
V
RFB A
RFB B
A1
C1
2
R2
1
OUT A
AD712
R7
2
10k
V
A2
AD712
R6
2
20k
V
PIN 15
R5
20k
V
R11
5k
V
A3
C2
2
R4
1
OUT B
AD712
AGND
AGND
2
R9
V
R10
2
20k
V
PIN 15
A2
AD712
R8
20k
V
R12
5k
V
AGND
OFFSET
GAIN
NOTE: ALL BYPASS CAPACITORS ARE 0.1
m
F
Figure 43. High Accuracy A/D Converter
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