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| 型號(hào)： | AD5263BRU20-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | 10 Bit, 65MSPS ADC, 1.8V, Int/Ext Ref, w/Power-Down 48-TQFP -40 to 85 |
| 中文描述： | QUAD 20K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24 |
| 封裝： | MO-153AD, TSSOP-24 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 84K |
| 代理商： | AD5263BRU20-REEL7 |
PRELIMINARY TECHNICAL DATA
Quad +15V Digital Potentiometers
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION
(V
DD
=
+
5V
,
V
SS
= -5V, V
L
= +5V,
V
A
= +V
DD
, V
B
= 0V, -40°C < T
A
< +125°C unless otherwise noted.)
Parameter
Symbol
Conditions
AD5263
08 AUG ’02, REV PrD
- 3 -
Min
Typ
1
Max
Units
SPI (DIS=’0’) INTERFACE TIMING CHARACTERISTICS applies to all parts (Notes 6,12)
Input Clock Pulse Width
t
CH
,t
CL
Data Setup Time
t
DS
Data Hold Time
t
DH
CLK to SDO Propagation Delay
13
t
PD
CS
Setup Time
t
CSS
CS
High Pulse Width
t
CSW
Reset Pulse Width
t
RS
CLK Fall to
CS
Rise Hold Time
t
CSH
CS
Rise to Clock Rise Setup
t
CS1
Clock level high or low
R
L
= 1K
, C
L
< 20pF
50
20
20
1
20
40
90
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
I
2
C (DIS=’1’) INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
SCL Clock Frequency
f
SCL
t
BUF
Bus free time between
STOP & START
t
1
t
HD;STA
Hold Time (repeated START)
t
2
t
LOW
Low Period of SCL Clock
t
3
t
HIGH
High Period of SCL Clock
t
4
t
SU;STA
Setup Time For START Condition t
5
t
HD;DAT
Data Hold Time
t
6
t
SU;DAT
Data Setup Time
t
7
t
F
Fall Time of both SDA & SCL signals
t
8
t
R
Rise Time of both SDA & SCL signals
t
9
t
SU;STO
Setup time for STOP Condition
t
10
After this period the first clock pulse is generated
0
1.3
0.6
1.3
0.6
0.6
0
100
0.6
400
0.9
300
300
KHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
NOTES:
1.
2.
Typicals represent average readings at +25°C and V
DD
= +5V, V
SS
= -5V.
Resistor position nonlinearity error R-INL is the deviation froman ideal value measured between the maximumresistance and the mnimumresistance wiper positions. R-DNL measures the
relative step change fromideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
=+5V, V
SS
=-5V.
V
AB
= V
DD
, Wiper (V
W
) = No connect
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider simlar to a voltage output D/A converter. VA = V
DD
and V
B
= 0V.
DNL specification limts of ±1LSB maximumare Guaranteed Monotonic operating conditions.
Resistor termnals A, B, W have no limtations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the Ax termnals. All Ax termnals are open circuited in shutdown mode.
Worst case supply current consumed when input all logic-input levels set at 2.4V, standard characteristic of CMOS logic.
PDISS is calculated from(IDD x VDD). CMOS logic level inputs result in mnimumpower dissipation.
All dynamc characteristics use V
DD
= +5V, V
SS
= -5V, V
L
= +5V
.
Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
See timng diagramfor location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed froma voltage level of 1.5V. Switching characteristics
are measured using V
L
= +5V.
Propagation delay depends on value of V
DD
, R
L
, and C
L
see applications text.
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89ml x 105ml, 9,345sq. ml.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
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| AD5263BRU200 | Preliminary Technical Data |
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