V
參數(shù)資料
型號(hào): AD5262BRUZ50-RL7
廠商: Analog Devices Inc
文件頁數(shù): 23/24頁
文件大?。?/td> 0K
描述: IC POT DUAL 50K 256POS 16TSSOP
標(biāo)準(zhǔn)包裝: 1,000
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型: 易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 4.5 V ~ 16.5 V,±4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
AD5260/AD5262
Rev. A | Page 8 of 24
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD5262
TOP VIEW
(Not to Scale)
W1
B1
VDD
SDI
CLK
SHDN
A1
W2
B2
A2
SDO
VL
VSS
CS
PR
GND
02
695
-00
9
Figure 8. AD5262 Pin Configuration
Table 6. AD5262 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SDO
Serial Data Output. Open-drain transistor requires a pull-up resistor.
2
A1
A Terminal RDAC 1.
3
W1
Wiper RDAC 1, Address A0 = 0.
4
B1
B Terminal RDAC 1.
5
VDD
Positive Power Supply. Specified for operation at both 5 V or 15 V. (Sum of |VDD| + |VSS| ≤ 15 V)
6
SHDN
Active Low Input. Terminal A, open-circuit. Shutdown controls variable Resistor 1 through Resistor R2.
7
CLK
Serial Clock Input, Positive Edge Triggered.
8
SDI
Serial Data Input.
9
CS
Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the
Address Bit A0, and loaded into the target RDAC register.
10
PR
Active Low Preset to Midscale. Sets RDAC registers to 0x80.
11
GND
Ground.
12
VSS
Negative Power Supply. Specified for operation at either 0 V or 5 V (sum of |VDD| + |VSS| < 15 V).
13
VL
Logic Supply Voltage. Needs to be same voltage as the digital logic controlling the AD5262.
14
B2
B Terminal RDAC 2.
15
W2
Wiper RDAC 2, Address A0 = 1.
16
A2
A Terminal RDAC 2.
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