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參數(shù)資料
| 型號(hào)： | AD5259EVAL |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 數(shù)字電位計(jì) |
| 英文描述： | Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer |
| 中文描述： | 非易失，I2C兼容256級(jí)，數(shù)字電位器 |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | AD5259EVAL |
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AD5259
Preliminary Technical Data
TIMING CHARACTERISTICS—5 k, 10 k, 50 k, 100 k VERSIONS
(V
DD
= +5V ± 10%, or +3V ± 10%; V
A
= V
DD
; V
B
= 0 V; –40°C < T
A
< +85°C; unless otherwise noted.)
Table 2.
Parameter
Symbol
I
2
C INTERFACE TIMING CHARACTERISTICS
1
(Specifications Apply to All Parts)
SCL Clock Frequency
f
SCL
t
BUF
Bus Free Time between STOP and START
t
1
t
HD;STA
Hold Time (Repeated START)
t
2
Rev. PrJ 7/22/04 | Page 4 of 14
Conditions
Min
0
1.3
0.6
Typ
Max
400
Unit
kHz
μs
μs
After this period, the first clock pulse is
generated.
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Repeated START Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL Signals
t
R
Rise Time of Both SDA and SCL Signals
t
SU;STO
Setup Time for STOP Condition
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1.3
0.6
0.6
0
100
0.6
0.9
300
300
μs
μs
μs
μs
ns
ns
ns
μs
t
1
SCL
SDA
P
S
P
0
t
3
t
2
t
8
t
9
t
8
t
9
t
4
t
5
t
7
t
6
t
10
Figure 4. I
2
C Interface Timing Diagram
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