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參數(shù)資料
| 型號： | AD5259BRMZ100-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer |
| 中文描述： | 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10 |
| 封裝： | 3 X 4.90 MM, 1.10 MM HEIGHT, LEAD FREE, MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大小： | 1039K |
| 代理商： | AD5259BRMZ100-R7 |
AD5259
ESD PROTECTION OF DIGITAL PINS AND
RESISTOR TERMINALS
The AD5259 V
DD
, V
LOGIC
, and GND power supplies define the
boundary conditions for proper 3-terminal and digital input
operation. Supply signals present on Terminal A, Terminal B,
and Terminal W that exceed V
DD
or GND are clamped by the
internal forward biased ESD protection diodes (see Figure 42).
Digital Input SCL and Digital Input SDA are clamped by ESD
protection diodes with respect to V
LOGIC
and GND as shown in
Figure 43.
Rev. A | Page 19 of 24
GND
A
W
B
V
DD
0
Figure 42. Maximum Terminal Voltages Set by V
DD
and GND
GND
SCL
SDA
V
LOGIC
0
Figure 43. Maximum Terminal Voltages Set by V
LOGIC
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 42), it
is important to power GND/V
DD
/V
LOGIC
before applying any
voltage to Terminal A, Terminal B, and Terminal W; otherwise,
the diode is forward biased, so the V
DD
and V
LOGIC
are powered
unintentionally and may affect the user’s circuit. The ideal power-
up sequence is in the following order: GND, V
DD
, V
LOGIC
, digital
inputs, and then V
A
, V
B
, V
V
A
, V
B
B
, V
W
, and the digital inputs is not important as long as
they are powered after GND/V
DD
/V
LOGIC
.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to use compact, minimum lead length layout
design. The leads to the inputs should be as direct as possible
with minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic capaci-
tors of 0.01 μF to 0.1 μF. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 44). The digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
V
DD
GND
V
DD
C2
10
μ
F
C1
0.1
μ
F
AD5259
+
0
Figure 44. Power Supply Bypassing
MULTIPLE DEVICES ON ONE BUS
The AD5259 has two configurable address pins, Pin AD0 and
Pin AD1. The state of these two pins is registered upon power-
up and decoded into a corresponding I
2
C-compatible 7-bit
address (see Table 5). This allows up to four devices on the bus
to be written to or read from independently.
EVALUATION BOARD
An evaluation board, with all necessary software, is available
to program the AD5259 from any PC running Windows 98/
2000/ XP. The graphical user interface, as shown in Figure 45,
is straightforward and easy to use. More detailed information
is available in the board’s user manual.
W
. The relative order of powering
0
Figure 45. AD5259 Evaluation Board Software
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