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參數(shù)資料
| 型號(hào)： | AD5254BRUZ50-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 27/32頁(yè) |
| 文件大小： | 0K |
| 描述： | IC POT DGTL QUAD 50K 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 650 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5253/AD5254
Data Sheet
Rev. C | Page 4 of 32
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD = 5 V, VSS = 0 V
2.4
V
DD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V
2.1
V
Input Logic Low
V
IL
V
DD = 5 V, VSS = 0 V
0.8
V
DD/VSS = +2.7 V/0 V or VDD/VSS = ±2.5 V
0.6
V
Output Logic High (SDA)
V
OH
R
PULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V
4.9
V
Output Logic Low (SDA)
V
OL
R
PULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V
0.4
V
WP Leakage Current
I
WP
WP = VDD
8
A
A0 Leakage Current
I
A0
A0 = GND
3
A
Input Leakage Current
(Other than WP and A0)
I
V
IN = 0 V or VDD
±1
A
Input Capacitance5
C
I
5
pF
POWER SUPPLIES
Single-Supply Power Range
V
DD
V
SS = 0 V
2.7
5.5
V
Dual-Supply Power Range
V
DD/VSS
±2.25
±2.75
V
Positive Supply Current
I
DD
V
IH = VDD or VIL = GND
5
15
A
Negative Supply Current
I
SS
V
IH = VDD or VIL = GND, VDD = 2.5 V,
V
SS = –2.5 V
–5
–15
A
EEMEM Data Storing Mode Current
I
DD_STORE
V
IH = VDD or VIL = GND
35
mA
EEMEM Data Restoring Mode
Current6
I
DD_RESTORE
V
IH = VDD or VIL = GND
2.5
mA
Power Dissipation7
P
DISS
V
IH = VDD = 5 V or VIL = GND
0.075
mW
Power Supply Sensitivity
PSS
ΔV
DD = 5 V ± 10%
0.025
+0.010
+0.025
%/%
ΔV
DD = 3 V ± 10%
–0.04
+0.02
+0.04
%/%
DYNAMIC CHARACTERISTICS5, 8
Bandwidth –3 dB
BW
R
AB = 1 k
4
MHz
Total Harmonic Distortion
THD
V
A =1 V rms, VB = 0 V, f = 1 kHz
0.05
%
V
W Settling Time
t
S
V
A = VDD, VB = 0 V
0.2
s
Resistor Noise Voltage
e
N_WB
R
WB = 500 , f = 1 kHz
(thermal noise only)
3
nV/√Hz
Digital Crosstalk
C
T
V
A = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change
–80
dB
Analog Coupling
C
AT
Signal input at A0 and measure the
output at W1, f = 1 kHz
–72
dB
1 Typical values represent average readings at 25°C and V
DD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the
relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 k version at VDD = 2.7 V,
IW = VDD/R for both VDD = 3 V and VDD = 5 V.
3 INL and DNL are measured at V
W with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 Command 0 NOP should be activated after Command 1 to minimize I
DD_RESTORE current consumption.
7 P
DISS is calculated from IDD × VDD = 5 V.
8 All dynamic characteristics use V
DD = 5 V.
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