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| 型號(hào)： | AD5254BRUZ1-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 30/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT QUAD 1K 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 1k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 650 ppm/°C |
| 存儲(chǔ)器類(lèi)型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD5253/AD5254
Rev. C | Page 7 of 32
INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
characteristics are measured using both VDD = 3 V and 5 V.
Table 3.
Parameter1
Symbol
Conditions
Min
Typ2
Max
Unit
INTERFACE TIMING
SCL Clock Frequency
fSCL
400
kHz
tBUF Bus-Free Time Between Stop and Start
t1
1.3
μs
tHD;STA Hold Time (Repeated Start)
t2
After this period, the first clock pulse is
generated.
0.6
μs
tLOW Low Period of SCL Clock
t3
1.3
μs
tHIGH High Period of SCL Clock
t4
0.6
μs
tSU;STA Set-up Time for Start Condition
t5
0.6
μs
tHD;DAT Data Hold Time
t6
0
0.9
μs
tSU;DAT Data Set-up Time
t7
100
ns
tF Fall Time of Both SDA and SCL Signals
t8
300
ns
tR Rise Time of Both SDA and SCL Signals
t9
300
ns
tSU;STO Set-up Time for Stop Condition
t10
0.6
μs
EEMEM Data Storing Time
tEEMEM_STORE
26
ms
EEMEM Data Restoring Time at Power-On3
tEEMEM_RESTORE1
VDD rise time dependent. Measure without
decoupling capacitors at VDD and VSS.
300
μs
EEMEM Data Restoring Time upon Restore
Command or Reset Operation3
tEEMEM_RESTORE2
VDD = 5 V.
300
μs
EEMEM Data Rewritable Time4
tEEMEM_REWRITE
540
μs
FLASH/EE MEMORY RELIABILITY
Endurance5
100
K cycles
Data Retention6, 7
100
Years
1 See Figure 23 for location of measured values.
2 Typical values represent average readings at 25°C and VDD = 5 V.
3 During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM restore time, whereas RDAC3 has the longest.
4 Delay time after power-on or reset before new EEMEM data to be written.
5 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and measured at –40°C, +25°C, and +105°C; typical endurance at +25°C is 700,000 cycles.
6 Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
7 When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I2C interface at these pins conducts a current of
about 0.8 mA at VDD = 5.5 V and 0.2 mA at VDD = 2.7 V.
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