參數(shù)資料
型號: AD524BE
廠商: ANALOG DEVICES INC
元件分類: 運動控制電子
英文描述: Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier
中文描述: INSTRUMENTATION AMPLIFIER, 100 uV OFFSET-MAX, 1 MHz BAND WIDTH, PQCC20
封裝: LCC-20
文件頁數(shù): 3/16頁
文件大?。?/td> 364K
代理商: AD524BE
REV. A
–3–
AD5241/AD5242
Parameter
Symbol
Conditions
Min
Typ
1
Max
Unit
INTERFACE TIMING CHARACTERISTICS (Applies to all parts.
5, 9
)
SCL Clock Frequency
t
BUF
Bus Free Time Between
STOP and START
t
HD; STA
Hold Time (Repeated START)
f
SCL
t
1
0
1.3
400
kHz
μ
s
t
2
After this period the first clock
pulse is generated.
600
ns
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU; STA
Setup Time for START Condition
t
HD; DAT
Data Hold Time
t
SU; DAT
Data Setup Time
t
R
Rise Time of Both
SDA and SCL Signals
t
F
Fall Time of Both SDA and SCL Signals t
9
t
SU; STO
Setup Time for STOP Condition
NOTES
1
Typicals represent average readings at 25
°
C, V
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 10 test circuit.
3
INL and DNL are measured at V
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 9 test circuit.
4
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
P
is calculated from (I
×
V
). CMOS logic level inputs result in minimum power dissipation.
7
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
8
All dynamic characteristics use V
= 5 V.
9
See timing diagram for location of measured values.
Specifications subject to change without notice.
t
3
t
4
t
5
t
6
t
7
t
8
1.3
0.6
600
μ
s
μ
s
ns
ns
ns
ns
50
900
100
300
300
ns
t
10
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